LTM4605IV#PBF Linear Technology, LTM4605IV#PBF Datasheet - Page 19

• Manufacturer Part Number: LTM4605IV#PBF
• Description: IC DC/DC UMODULE 5A 141-LGA
• Manufacturer: Linear Technology
• Series: µModuler
• Type: Point of Load (POL) Non-Isolatedr

Specifications of LTM4605IV#PBF

• Design Resources: LTM4605 Spice Model
• Output: 0.8 ~ 16 V
• Number Of Outputs: 1
• Power (watts): 80W
• Mounting Type: Surface Mount
• Voltage - Input: 4.5 ~ 20V
• Package / Case: 141-LGA
• 1st Output: 0.8 ~ 16 VDC @ 5A
• Size / Dimension: 0.59" L x 0.59" W x 0.11" H (15mm x 15mm x 2.8mm)
• Power (watts) - Rated: 80W
• Operating Temperature: -40°C ~ 85°C
• Efficiency: 98%
• Dc To Dc Converter Type: Non-Inverting/Inverting/Step Up/Step Down
• Pin Count: 141
• Input Voltage: 20V
• Output Voltage: 0.8 to 16V
• Switching Freq: 170 TO 440KHz
• Output Current: 12/5A
• Package Type: LGA
• Output Type: Adjustable
• Switching Regulator: Yes
• Load Regulation: 0.5%
• Line Regulation: 0.02%
• Mounting: Surface Mount
• Input Voltage (min): 4.5V
• Operating Temperature Classification: Industrial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• 3rd Output: -
• 2nd Output: -
• Lead Free Status / Rohs Status: Compliant

APPLICATIONS INFORMATION
Layout Checklist/Example
The high integration of LTM4605 makes the PCB board
layout very simple and easy. However, to optimize its electri-
cal and thermal performance, some layout considerations
are still necessary.
• Use large PCB copper areas for high current path, includ-
• Place high frequency input and output ceramic capaci-
• Route SENSE
ing V
minimize the PCB conduction loss and thermal stress.
tors next to the V
high frequency noise
PC trace spacing. Avoid sense lines passing through
noisy areas, such as switch nodes.
IN
, R
SENSE
–
and SENSE
, SW1, SW2, PGND and V
IN
, PGND and V
+
leads together with minimum
SW1
V
PGND
OUT
C
OUT
OUT
pins to minimize
OUT
Figure 13. Recommended PCB Layout
. It helps to
KELVIN CONNECTIONS TO R
+
L1
–
R
SENSE
SGND
SW2
• Place a dedicated power ground layer underneath the
• To minimize the via conduction loss and reduce module
• Do not put vias directly on pads, unless the vias are
• Use a separated SGND ground copper area for com-
Figure 13. gives a good example of the recommended
layout.
unit.
thermal stress, use multiple vias for interconnection
between the top layer and other power layers
capped.
ponents connected to signal pins. Connect the SGND
to PGND underneath the unit.
V
SENSE
IN
R
SENSE
PGND
C
IN
4605 F13
LTM4605
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