STEVAL-PCC010V1 STMicroelectronics, STEVAL-PCC010V1 Datasheet - Page 48

• Manufacturer Part Number: STEVAL-PCC010V1
• Description: BOARD EVAL FOR ST802RT1
• Manufacturer: STMicroelectronics

Specifications of STEVAL-PCC010V1

• Main Purpose: Interface, Ethernet Controller (PHY and MAC)
• Embedded: Yes, MCU, 8-Bit
• Utilized Ic / Part: ST802RT1
• Primary Attributes: 1 Port, 100BASE-TX/10BASE-T
• Secondary Attributes: MII, RMII
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-10360

Device operation
7.22
7.23
Table 33.
48/58
WRITE
READ
Far-end-fault
For 100Base-FX mode (which does not support auto-negotiation), the ST802RT1x
implements the IEEE 802.3 standard far-end-fault mechanism for the indication and
detection of remote error conditions. If the far-end-fault is enabled, a PHY transmits the far-
end-fault indication whenever a receive channel failure is detected. Each PHY also
continuously monitors the receive channel when a valid signal is present.
When its link partner is indicating a remote error, the PHY forces its link monitor into the link
fail state and sets the remote fault bit in the status register. The far-end-fault is on by default
in 100BaseFX, off by default in 100Base-TX and 10Base-T modes, and may be controlled
by software and reset.
MII management interface
Internal register access is guaranteed through the MII management interface, as specified
in the IEEE 802.3u standard, Clause 22.
This serial interface consists of a Management Data Clock (MDC) pin and a Management
Data I/O (MDIO) pin. The MDC pin is always driven by the station management entity (STA)
while the MDIO pin can be driven by either the STA or the PHY, depending on the operation
in progress. The logic value on the MDIO pin is sampled on the rising edge of the MDC clock
signal.
The MDIO pin has an internal pull-up used to keep the line to logic 1 when not driven.
Register read/write operations are performed, sending on the MII Management interface
frames in the format shown in
Management frame format
Both read/write frames start with a preamble (PRE) composed of 32 consecutive logic 1s on
the MDIO pin and corresponding 32 clock cycles on the MDC pin. The management frame
preamble can be suppressed, as described in
The preamble is followed by a 2-bit start of frame (ST), consisting of a transition to logic 0
and then back to logic 1, after which the operation code (OP) is transmitted to distinguish
between read and write operations.
After the operation code, the PHY address (PHYAD) and register address (REGAD) are
sent, each composed of 5 bits which have to be sent MSB first.
The turn-around (TA) is a 2-bit time spacing placed between the register address and the
data field inserted to avoid contention during a read transaction. In a write operation, the
STA drives a logic 1 during the first bit time and a logic 0 during the second one. In a read
operation, both STA and PHY are in high impedance during the first bit time and then the
PHY drives 0 during the second one.
The data field contains the 16 bits to write to, or read from, the specified register and is
followed by at least one IDLE bit which closes the frame.
1…1
1…1
PRE
ST
01
01
OP
10
01
Table
Doc ID 17049 Rev 1
PHYAD
AAAAA
AAAAA
33.
Section
REGAD
RRRRR
RRRRR
7.13.
TA
Z0
10
ST802RT1A, ST802RT1B
DATA
D…D
D…D
IDLE
Z
Z