EVAL-ADN2850-25EBZ Analog Devices Inc, EVAL-ADN2850-25EBZ Datasheet - Page 11

• Manufacturer Part Number: EVAL-ADN2850-25EBZ
• Description: BOARD EVALUATION FOR ADN2850-25
• Manufacturer: Analog Devices Inc

Specifications of EVAL-ADN2850-25EBZ

• Main Purpose: Digital Potentiometer
• Utilized Ic / Part: ADN2850-35
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

TERMINAL VOLTAGE OPERATING RANGE
The ADN2850 positive V
defines the boundary conditions for proper two-terminal program-
mable resistance operation. Supply signals present on terminals W
and B that exceed V
forward biased diodes (see Figure 7).
The ground pin of the ADN2850 device is primarily used as a digital
ground reference that needs to be tied to the PCB’s common
ground. The digital input control signals to the ADN2850 must
be referenced to the device ground pin (GND), and satisfy the
logic level defined in the Specifications table of this data sheet.
An internal level shift circuit ensures that the common-mode
voltage range of the two terminals extends from V
regardless of the digital input level. In addition, there is no
polarity constraint on voltage across terminals W and B. The
magnitude of |V
Power-Up Sequence
Since diodes limit the voltage compliance at terminals B and W
(see Figure 7) it is important to power V
ing any voltage to terminals B and W. Otherwise, the diode will be
forward biased such that V
For example, applying 5 V across V
to exhibit 4.3 V. Although it is not destructive to the device, it may
affect the rest of the user’s system. As a result, the ideal power-up
sequence is in the following order: GND, V
and V
important as long as they are powered after V
Regardless of the power-up sequence and the ramp rates of the
power supplies, once V
remains effective, which retrieves EEMEM saved values to the
RDAC registers (see TPC 7).
Layout and Power Supply Bypassing
It is a good practice to employ compact, minimum-lead length
layout design. The leads to the input should be as direct as pos-
sible with a minimum of conductor length. Ground paths should
have low resistance and low inductance. To minimize the digital
ground bounce, the digital signal ground reference can be joined
remotely to the analog ground terminal of the ADN2850.
Similarly, it is also a good practice to bypass the power supplies
with quality capacitors for optimum stability. Supply leads to the
device should be bypassed with 0.01 µF to 0.1 µF disc or chip
ceramics capacitors. Low ESR 1 µF to 10 µF tantalum or electro-
lytic capacitors should also be applied at the supplies to minimize
any transient disturbance (see Figure 8).
REV. B
Figure 7. Maximum Terminal Voltages Set by V
B/W
. The order of powering V
WB
| is bounded by V
DD
DD
or V
DD
/V
DD
SS
SS
/V
and negative V
will be clamped by the internal
SS
are powered, the power-on reset
will be powered unintentionally.
B
DD
, V
DD
will cause the V
W
DD
, and Digital Inputs is not
– V
/V
DD
SS
DD
SS
SS
, V
.
first before apply-
/V
power supply
SS
SS
V
W
B
V
, Digital Inputs,
DD
SS
SS
.
to V
DD
DD
terminal
and V
DD
SS
–11–
RDAC STRUCTURE
The patent-pending RDAC contains a string of equal resistor
segments, with an array of analog switches, that act as the wiper
connection. The number of positions is the resolution of the
device. The ADN2850 has 1024 connection points, allowing it to
provide better than 0.1% setability resolution. Figure 9 shows an
equivalent structure of the connections between the two terminals
that make up one channel of the RDAC. The S
ON, while one of the switches SW(0) to SW(2
one at a time depending on the resistance position decoded from
the data bits. Since the switch is not ideal, there is a 50 Ω wiper
resistance, R
and temperature. The lower the supply voltage or the higher the
temperature, the higher the resulting wiper resistance. Users
should be aware of the wiper resistance dynamics if accurate
prediction of the output resistance is needed.
Device Resolution
1024-Step
CALCULATING THE PROGRAMMABLE RESISTANCE
The nominal full-scale resistance of the RDAC between terminals
W and B, R
positions (10-bit resolution). The final digits of the part number
determine the nominal resistance value, e.g., 25 kΩ = 25 and
250 kΩ = 250.
The 10-bit data-word in the RDAC latch is decoded to select one
of the 1024 possible settings. The following discussion describes
the calculation of resistance R
part. The wiper’s first connection starts at the B terminal for
data 000
is independent of the full-scale resistance. The second connection
is the first tap point where R
Table VII. Nominal Individual Segment Resistor Values
H
. R
WB_FS
Figure 9. Equivalent RDAC Structure
W
V
V
WB
Figure 8. Power Supply Bypassing
DD
SS
. Wiper resistance is a function of supply voltage
(0) is 50 Ω because of the wiper resistance and it
, is available with 25 kΩ and 250 kΩ with 1024
10 F
10 F
R
DIGITAL
CIRCUITRY
OMITTED FOR
CLARITY
S
C3
C4
REGISTER
DECODER
= R
WIPER
RDAC
AND
WB
+
+
0.1 F
0.1 F
/ 2
N
C1
C2
WB
25 kΩ
24.4
WB
(1) becomes 24.4 Ω + 50 = 74.4 Ω
R
R
R
(D) at different codes of a 25 kΩ
S
S
S
SW(2
SW(2
SW(1)
SW(0)
SWB
V
V
DD
SS
N –
N –
ADN2850
2)
1)
GND
W
B
ADN2850
N
WB
– 1) will be ON
250 kΩ
244
will always be