EVAL-ADN2850-25EBZ Analog Devices Inc, EVAL-ADN2850-25EBZ Datasheet - Page 9

• Manufacturer Part Number: EVAL-ADN2850-25EBZ
• Description: BOARD EVALUATION FOR ADN2850-25
• Manufacturer: Analog Devices Inc

Specifications of EVAL-ADN2850-25EBZ

• Main Purpose: Digital Potentiometer
• Utilized Ic / Part: ADN2850-35
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

conditions. Table IV illustrates the operation of the shifting
function on the individual RDAC register data bits. Each line
going down the table represents a successive shift operation. Note
that the left shift 12 and 13 commands were modified such that
if the data in the RDAC register is equal to zero, and the data is
left shifted, the RDAC register is then set to code 1. Similarly, if the
data in the RDAC register is greater than or equal to midscale,
and the data is left shifted, then the data in the RDAC register is
automatically set to full scale. This makes the left shift function
as ideal a logarithmic adjustment as possible.
The right shift 4 and 5 commands will be ideal only if the LSB is
zero (i.e., ideal logarithmic—no error). If the LSB is a one, then
the right shift function generates a linear half LSB error, which
translates to a number of bits-dependent logarithmic error as
shown in Figure 3. The plot shows the error of the odd numbers
of bits for ADN2850.
Actual conformance to a logarithmic curve between the data con-
tents in the RDAC register and the wiper position for each right
shift 4 and 5 command execution contains an error only for odd
numbers of bits. Even numbers of bits are ideal. The graph in
Figure 3 shows plots of Log_Error [i.e., 20
ADN2850. For example, code 3 Log_Error = 20
= –15.56 dB, which is the worst case. The plot of Log_Error is
more significant at the lower codes.
REV. B
Table IV. Detail Left and Right Shift Functions for 6 dB
Step Increment and Decrement
Figure 3. Plot of Log_Error Conformance for Odd
Numbers of Bits Only (Even Numbers of Bits Are Ideal)
Left Shift
6 dB/step
–20
–40
–60
–80
0
0
0.1
Left Shift
00 0000 0000
00 0000 0001
00 0000 0010
00 0000 0100
00 0000 1000
00 0001 0000
00 0010 0000
00 0100 0000
00 1000 0000
01 0000 0000
10 0000 0000
11 1111 1111
11 1111 1111
0.2
CODE – From 1 to 1023 by 2.0
0.3
0.4
0.5
Right Shift
11 1111 1111
01 1111 1111
00 1111 1111
00 0111 1111
00 0011 1111
00 0001 1111
00 0000 1111
00 0000 0111
00 0000 0011
00 0000 0001
00 0000 0000
00 0000 0000
00 0000 0000
0.6
0.7
0.8
10
log
3
0.9
10
Right Shift
–6 dB/step
(error/code)]
log
1.0
10
1.1
(0.5/3)
–9–
Using Additional Internal Nonvolatile EEMEM
The ADN2850 contains additional internal user storage registers
(EEMEM) for saving constants and other 16-bit data. Table V
provides an address map of the internal storage registers shown
in the functional block diagram as EEMEM1, EEMEM2, and
and 26 bytes (13 addresses
EEMEM
Number
1
2
3
4
:
15
16
NOTES
1
2
3
4
Calculating Actual Full-Scale Resistance
The actual tolerance of the rated full-scale resistance R
stored in EEMEM register 15 during factory testing. The actual
full-scale resistance can therefore be calculated, which will be
valuable for tolerance matching or calibration. Notice this value
is read only, and the full-scale resistance of R
R
The tolerance in % is stored in the last 16 bits of data in EEMEM
register 15. The format is sign magnitude binary format with the
MSB designates for sign (0 = positive and 1 = negative), the next
7 MSB designate for the integer number, and the 8 LSB designate
for the decimal number. See Table VI.
Table VI. Tolerance in % from Rated Full-Scale Resistance
For example, if R
1100 0000 1111, R
Thus, R
Read only.
RDAC data stored in EEMEM locations are transferred to their corresponding
RDAC REGISTER at power-on, or when instructions 1, 8, and PR are executed.
Execution of instruction 1 leaves the device in the read mode power consumption
state. After the last instruction 1 is executed, the user should perform a NOP,
instruction 0 to return the device to the low power idling state.
USER <data> are internal nonvolatile EEMEM registers available to store and
retrieve constants and other 16-bit information using instructions 3 and 9 respectively.
WB1_FS,
mag
MSB:
Next 7 MSB:
8 LSB:
% Tolerance = +28.06%
sign
Bit
D15
sign
Sign
D14
WB_FS_ACTUAL
2
of typically 0.1%.
6
7 Bits for Integer Number Decimal
D13
2
5
D12
2
Table V. EEMEM Address Map
4
D11
WB_FS_RATED
2
Address
0000
0001
0010
0011
:
1110
1111
0 = Positive
001 1100 = 28
0000 1111 = 15
3
WB_FS_ACTUAL
D10
2
= 320.15 kΩ
2
D9
2
1
D8
2
0
= 250 kΩ and the data is 0001
2 bytes each) of USER EEMEM.
Point
•
can be calculated as follows:
D7
2
-1
8 Bits for Decimal Number
D6
2
2
-2
–8
EEMEM Content For
RDAC1
RDAC2
USER1
USER2
:
USER13
% Tolerance
D5
2
-3
= 0.06
D4
2
-4
WB2_FS
ADN2850
D3
2
-5
3
1, 2
D2
2
-6
matches
4
2
D1
-7
WB1
2
D0
-8
is