EVAL-ADN2850-25EBZ Analog Devices Inc, EVAL-ADN2850-25EBZ Datasheet - Page 17

• Manufacturer Part Number: EVAL-ADN2850-25EBZ
• Description: BOARD EVALUATION FOR ADN2850-25
• Manufacturer: Analog Devices Inc

Specifications of EVAL-ADN2850-25EBZ

• Main Purpose: Digital Potentiometer
• Utilized Ic / Part: ADN2850-35
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

The output voltage represents the average incoming optical power.
The output voltage of the log stage does not have to be accurate
from device to device, as the responsivity of the photodiode will
change between devices. An op amp stage is shown after the log
amp stage, which compensates for V
Equation 4 is ideal. If the reference current is 1 mA at room
temperature, characterization shows that there is an additional
30 mV offset between V
Such offset is believed to be caused by the transistors self-heating
and the thermal gradient effect. As seen in Figure 13, the error
between an approximation and the actual performance ranges is
less than 0% to –4% from 0.1 mA to 0.1 A.
Resistance Scaling
The ADN2850 offers either 25 kΩ or 250 kΩ full-scale resistance.
Users who need lower resistance and still maintain the numbers
of step adjustment can parallel two or more devices. Figure 14
shows a simple scheme of paralleling both channels of the pro-
grammable resistors. In order to adjust half of the resistance
linearly per step, users need to program both devices coherently
with the same settings. Note that since the devices will be pro-
grammed one after another, an intermediate state will occur, and
this method may not be suitable for certain applications.
REV. B
V
2 —
0.30
0.25
0.20
0.15
0.10
0.05
Figure 13. Typical V
and T
1.E-07
0
V = 0.026
1
A
= 25 ° C
1.E-06
×
In
2
DEVICE 1
DEVICE 2
DEVICE 3
CURVE FIT
and V



0.001
I
PD
2
1.E-05
I
1
PD
– V
. A curve fit approximation yields

 +

– A
1
T
vs. I
0 03
variation over temperature.
.
I
T
PD
REF
A
1.E-04
= 25 C
at I
= 1mA
ERROR
REF
= 1 mA
1.E-03
12
–3
–6
9
6
3
0
(5)
–17–
Much lower resistance can also be achieved by paralleling a
discrete resistor as shown in Figure 15.
The equivalent resistance at a given setting is approximated as:
In this approach, the adjustment is not linear but pseudo-
logarithmic. Users should be aware of the need for tolerance matching
as well as temperature coefficient matching of the components.
The internal parasitic capacitances and the external capacitive
loads dominate the ac characteristics of the RADCs. A general
parasitic simulation model is shown in Figure 16.
Listing I provides a macro model net list for the 25 kΩ RDAC:
.PARAM D = 1024, RDAC = 25E3
*
.SUBCKT RDAC (W, B)
*
RWB W B {D/1024
CW W 0 80E-12
CB B 0 11E-12
*
.ENDS RDAC
Figure 16. RDAC Circuit Simulation Model (RDAC = 25 k Ω )
R =
Figure 15. Resistor Scaling with Pseudo-Log Taper
Adjustment Characteristics
Figure 14. Reduce Resistance by Half with Linear
Adjustment Characteristics
eq
Listing I. Macro Model Net List for RDAC
D R
×
BASIC RDAC SPICE MODEL
WB FS
D R
×
_
RDAC
25k
RDAC
W
B1
B1
WB_FS
+
C
W
51200 1024
= 80pF
W1
+
W1
51200
50}
B2
+
C
B
R
W2
= 11pF
B
×
R
ADN2850
(6)