EVAL-ADN2850-25EBZ Analog Devices Inc, EVAL-ADN2850-25EBZ Datasheet - Page 15

• Manufacturer Part Number: EVAL-ADN2850-25EBZ
• Description: BOARD EVALUATION FOR ADN2850-25
• Manufacturer: Analog Devices Inc

Specifications of EVAL-ADN2850-25EBZ

• Main Purpose: Digital Potentiometer
• Utilized Ic / Part: ADN2850-35
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

resistor and the capacitive loading at the SDO-to-SDI interface may
require additional time delay between subsequent devices.
When two ADN2850s are daisy-chained, 48 bits of data are
required. The first 24 bits (formatted 4-bit command, 4-bit
address, and 16-bit data) go to U2, and the second 24 bits with
the same format go to U1. Keep CS low until all 48 bits are
clocked into their respective serial registers. CS is then pulled
high to complete the operation.
TERMINAL VOLTAGE OPERATING RANGE
The positive V
define the boundary conditions for proper 2-terminal digital
resistor operation. Supply signals present on Terminal B, and
Terminal W that exceed V
forward-biased diodes (see Figure 29).
The GND pin of the ADN2850 is primarily used as a digital
ground reference. To minimize the digital ground bounce,
the ADN2850 ground terminal should be joined remotely to
the common ground (see Figure 30). The digital input control
signals to the ADN2850 must be referenced to the device
ground pin (GND) and must satisfy the logic level defined in
the Specifications section. An internal level-shift circuit ensures
that the common-mode voltage range of the three terminals
CONTROLLER
MICRO-
SCLK SS
Figure 29. Maximum Terminal Voltages Set by V
MOSI
Figure 28. Daisy-Chain Configuration Using SDO
DD
and negative V
SDI
ADN2850
CS
U1
DD
CLK
or V
SDO
SS
SS
power supplies of the ADN2850
are clamped by the internal
V
DD
R
2.2kΩ
P
SDI
CS
V
ADN2850
V
W
B
SS
DD
DD
U2
and V
CLK
SDO
SS
Rev. C | Page 15 of 28
extends from V
Power-Up Sequence
Because there are diodes to limit the voltage compliance at
Terminal B, and Terminal W (see Figure 29), it is important to
power V
B, and Terminal W. Otherwise, the diode is forward-biased such
that V
applying 5 V across Terminal W and Terminal B prior to V
causes the V
the device, but it might affect the rest of the user’s system. The
ideal power-up sequence is GND, V
and V
inputs is not important as long as they are powered after V
and V
Regardless of the power-up sequence and the ramp rates of the
power supplies, when V
preset activates, which restores the EEMEM values to the RDAC
registers.
Layout and Power Supply Bypassing
It is a good practice to employ compact, minimum lead-length
layout design. The leads to the input should be as direct as
possible with a minimum conductor length. Ground paths
should have low resistance and low inductance.
Similarly, it is good practice to bypass the power supplies with
quality capacitors for optimum stability. Bypass supply leads to
the device with 0.01 μF to 0.1 μF disk or chip ceramic capacitors.
Also, apply low ESR, 1 μF to 10 μF tantalum or electrolytic
capacitors at the supplies to minimize any transient disturbance
(see Figure 30).
DD
B
SS
, and V
.
V
V
DD
and V
DD
SS
and V
DD
10µF
10µF
W
SS
C3
C4
terminal to exhibit 4.3 V. It is not destructive to
SS
. The order of powering V
are powered unintentionally. For example,
SS
to V
Figure 30. Power Supply Bypassing
+
+
first before applying any voltage to Terminal
0.1µF
0.1µF
DD
C1
C2
DD
, regardless of the digital input level.
and V
SS
are powered, the power-on
DD
V
V
DD
SS
and V
ADN2850
GND
B
, V
SS
W
, digital inputs,
, and the digital
ADN2850
DD
DD