LM25069MM-2EVAL National Semiconductor, LM25069MM-2EVAL Datasheet - Page 12

BOARD EVALUATION LM25069

LM25069MM-2EVAL

Manufacturer Part Number
LM25069MM-2EVAL
Description
BOARD EVALUATION LM25069
Manufacturer
National Semiconductor
Datasheets

Specifications of LM25069MM-2EVAL

Main Purpose
Power Management, Hot Swap Controller
Embedded
No
Utilized Ic / Part
LM25069-2
Primary Attributes
High Side MOSFET Driver, Inrush Current Limiting
Secondary Attributes
Auto Restart, 2.9 V ~ 17 V Supply
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Under-Voltage Lock-Out (UVLO)
The series pass MOSFET (Q1) is enabled when the input
supply voltage (V
the programmable under-voltage lockout (UVLO) and over-
voltage lock-out (OVLO) levels. Typically the UVLO level at
V
1. Refering to the Block Diagram when V
LO level, the internal 20 µA current source at UVLO is en-
abled, the current source at OVLO is off, and Q1 is held off
by the 2 mA pull-down current at the GATE pin. As V
increased, raising the voltage at UVLO above its threshold the
20 µA current source at UVLO is switched off, increasing the
voltage at UVLO, providing hysteresis for this threshold. With
the UVLO pin above its threshold, Q1 is switched on by the
20 µA current source at the GATE pin if the insertion time
delay has expired. See the Applications Section for a proce-
dure to calculate the values of the threshold setting resistors
(R1-R3). The minimum possible UVLO level at V
set by connecting the UVLO pin to VIN. In this case Q1 is
enabled after the insertion time.
Over-Voltage Lock-Out (OVLO)
The series pass MOSFET (Q1) is enabled when the input
supply voltage (V
the programmable under-voltage lockout (UVLO) and over-
voltage lock-out (OVLO) levels. If V
voltage above its threshold Q1 is switched off by the 2 mA
pull-down current at the GATE pin, denying power to the load.
When the OVLO pin is above its threshold, the internal 20 µA
current source at OVLO is switched on, raising the voltage at
OVLO to provide threshold hysteresis. When V
below the OVLO level Q1 is enabled. See the Applications
Section for a procedure to calculate the threshold setting re-
sistor values.
Shutdown Control
The load current can be remotely switched off by taking the
UVLO pin below its threshold with an open collector or open
SYS
is set with a resistor divider (R1-R3) as shown in
SYS
SYS
) is within the operating range defined by
) is within the operating range defined by
SYS
raises the OVLO pin
SYS
FIGURE 5. Restart Sequence (LM25069-2)
is below the UV-
SYS
SYS
is reduced
can be
Figure
SYS
is
12
drain device, as shown in
pin the LM25069 switches on the load current with in-rush
current and power limiting.
Power Good Pin
The Power Good indicator pin (PGD) is connected to the drain
of an internal N-channel MOSFET capable of sustaining 17V
in the off-state, and transients up to 20V. An external pull-up
resistor is required at PGD to an appropriate voltage to indi-
cate the status to downstream circuitry. The off-state voltage
at the PGD pin can be higher or lower than the voltages at
VIN and OUT. PGD is switched high when the voltage from
SENSE to OUT (the external MOSFET’s V
low 1.3V. PGD switches low when the MOSFET’s V
increased past 1.9V. If the UVLO pin is taken below its thresh-
old or the OVLO pin taken above its threshold, to disable the
LM25069, PGD switches low within 10 µs without waiting for
the voltage at OUT to fall. The PGD output pin is high when
the voltage at VIN is less than 1.6V.
FIGURE 6. Shutdown Control
Figure
6. Upon releasing the UVLO
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DS
) decreases be-
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DS
is

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