LM25069MM-2EVAL National Semiconductor, LM25069MM-2EVAL Datasheet - Page 18

• Manufacturer Part Number: LM25069MM-2EVAL
• Description: BOARD EVALUATION LM25069
• Manufacturer: National Semiconductor

Specifications of LM25069MM-2EVAL

• Main Purpose: Power Management, Hot Swap Controller
• Embedded: No
• Utilized Ic / Part: LM25069-2
• Primary Attributes: High Side MOSFET Driver, Inrush Current Limiting
• Secondary Attributes: Auto Restart, 2.9 V ~ 17 V Supply
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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V
at PGD as shown in
be as high as 17V, and can be higher or lower than the volt-
ages at VIN and OUT.
Design-in Procedure
The recommended design-in procedure is as follows:
•
•
•
•
•
DS
Determine the current limit threshold (I
must be higher than the normal maximum load current,
allowing for tolerances in the current sense resistor value
and the LM25069 Current Limit threshold voltage. Use
equation 1 to determine the value for R
Determine the maximum allowable power dissipation for
the series pass FET (Q1), using the device’s SOA
information. Use equation 2 to determine the value for
R
Determine the value for the timing capacitor at the TIMER
pin (C
period (t
time. The turn-on time can be estimated using the
equations in the TURN-ON TIME section of this data
sheet, but should be verified experimentally. Review the
resulting insertion time, and restart timing if the
LM25069-2 is used.
Choose option A, B, C, or D from the UVLO, OVLO section
of the Application Information for setting the UVLO and
OVLO thresholds and hysteresis. Use the procedure for
the appropriate option to determine the resistor values at
the UVLO and OVLO pins.
Choose the appropriate voltage, and pull-up resistor, for
the Power Good output.
of Q1 increases above 1.9V. A pull-up resistor is required
PWR
.
T
) using equation 3 or equation 4. The fault timeout
FAULT
FIGURE 14. Power Good Output
) must be longer than the circuit’s turn-on-
Figure
14. The pull-up voltage (V
FIGURE 15. Adding Delay to the Power Good Output Pin
LIM
S
.
). This threshold
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PGD
) can
18
If a delay is required at PGD, suggested circuits are shown in
Figure
ing edge, but not to the falling edge. In
edge is delayed by R
edge is delayed a lesser amount by R
diode across R
two edges, or a short delay at the rising edge and a long delay
at the falling edge.
PC Board Guidelines
The following guidelines should be followed when designing
the PC board for the LM25069:
•
•
•
•
•
•
•
Place the LM25069 close to the board’s input connector
to minimize trace inductance from the connector to the
FET.
Place a small capacitor (1000 pF) directly adjacent to the
VIN and GND pins of the LM25069 to help minimize
transients which may occur on the input supply line.
Transients of several volts can easily occur when the load
current is shut off.
The sense resistor (R
and connected to it using the Kelvin techniques shown in
Figure
The high current path from the board’s input to the load
(via Q1), and the return path, should be parallel and close
to each other to minimize loop inductance.
The ground connection for the various components
around the LM25069 should be connected directly to each
other, and to the LM25069’s GND pin, and then connected
to the system ground at one point. Do not connect the
various component grounds to each other through the high
current ground line.
Provide adequate heat sinking for the series pass device
(Q1) to help reduce stresses during turn-on and turn-off.
The board’s edge connector can be designed to shut off
the LM25069 as the board is removed, before the supply
15. In
7.
Figure
PG2
(Figure
15a, capacitor C
PG1
S
) should be close to the LM25069,
+ R
15c) allows for equal delays at the
PG2
and C
PG
PG2
Figure
adds delay to the ris-
PG
and C
, while the falling
15b, the rising
PG
. Adding a
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