KIT33879AEKEVBE Freescale Semiconductor, KIT33879AEKEVBE Datasheet - Page 11

• Manufacturer Part Number: KIT33879AEKEVBE
• Description: BOARD EVALUATION FOR MC33879
• Manufacturer: Freescale Semiconductor
• Type: PWM Controllersr

Specifications of KIT33879AEKEVBE

• Main Purpose: Power Management, High & Low Side Driver (Internal FET)
• Embedded: No
• Utilized Ic / Part: MC33879
• Primary Attributes: 8-output hardware-configurable
• Secondary Attributes: 16-bit serial input control
• Interface Type: SPI
• Product: Power Management Modules
• Silicon Manufacturer: Freescale
• Silicon Core Number: MC33879
• Kit Application Type: Power Management
• Application Sub Type: Switch
• Kit Contents: Board, CD
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: MC33879

Table 5. Dynamic Electrical Characteristics (continued)
Where applicable, typical values reflect the parameter’s approximate average value with V
DIGITAL INTERFACE TIMING
Notes
Analog Integrated Circuit Device Data
Freescale Semiconductor
Recommended Frequency of SPI Operation
Falling Edge of CS to Rising Edge of SCLK (Required Setup Time)
Falling Edge of SCLK to Rising Edge of CS (Required Setup Time)
DI to Falling Edge of SCLK (Required Setup Time)
Falling Edge of SCLK to DI (Required Hold Time)
DI, CS, SCLK Signal Rise Time
DI, CS, SCLK Signal Fall Time
Time from Falling Edge of CS to DO Low-impedance
Time from Rising Edge of CS to DO High-impedance
Time from Rising Edge of SCLK to DO Data Valid
14.
15.
16.
17.
18.
Characteristics noted under conditions 3.1 V ≤ V
This parameter is guaranteed by design. Production test equipment uses 4.16 MHz, 5.5 V/3.1 V SPI interface.
Rise and Fall time of incoming DI, CS, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing.
Time required for output status data to be available for use at DO pin.
Time required for output status data to be terminated at DO pin.
Time required to obtain valid data out from DO following the rise of SCLK.
SCLK
DO
CS
DI
0.2 V
DD
(14)
(15)
Characteristic
(15)
0.7 V
0.2 V
t
DO(EN)
DD
DD
t
LEAD
0.7 V
0.2 V
0.7 V
0.2 V
DD
DD
DD
DD
(14)
t
DI(SU)
MSB in
MSB out
(18)
(16)
Figure 4. SPI Timing Diagram
(17)
t
DI(HOLD)
DD
TIMING DIAGRAMS
≤ 5.5 V, 5.5 V ≤ V
PWR
t
Symbol
t
DI (HOLD)
t
t
DO (DIS)
t
DO (EN)
t
t
t
DI (SU)
t
VALID
≤ 18 V, - 40°C ≤ T
LEAD
f
R (DI)
F (DI)
LAG
SPI
t
VALID
Min
100
50
16
20
–
–
–
–
–
–
PWR
C
≤ 125°C, unless otherwise noted.
ELECTRICAL CHARACTERISTICS
= 13 V, T
Typ
4.0
5.0
5.0
LSB out
25
–
–
–
–
–
–
t
LAG
A
= 25°C.
TIMING DIAGRAMS
Max
t
55
55
55
DO(DIS)
–
–
–
–
–
–
–
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
33879
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