SERDES03-40USB/NOPB National Semiconductor, SERDES03-40USB/NOPB Datasheet - Page 3

• Manufacturer Part Number: SERDES03-40USB/NOPB
• Description: KIT EVALUATION FOR DS99R103/104
• Manufacturer: National Semiconductor

Specifications of SERDES03-40USB/NOPB

• Main Purpose: Interface, Serializer, Deserializer (SERDES)
• Utilized Ic / Part: DS99R103, DS99R104
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -
• Other names: SERDES03-40USB

DS90C241Q
DS90C124Q
DS90UR241Q
DS90UR124Q
DS99R421Q
DS90UR905Q
In this example, if the PCLK was at 43MHz, the serial trans-
mission rate is 28 times the PCLK, or 1.2 Gbps. The user data
rate is 24X of PCLK, or 1.0 Gbps in this example.
Signal Quality Enhancers
As noted above, the data payload is modified to randomize,
scramble, and balance the data to support AC-coupling of the
interface and to also enhance the signal quality of the serial
signal. In addition to these, the physical layer is also en-
hanced and allows for various options depending upon the
chipset.
Certain FPD-Link II line drivers feature an adjustable Pre-
Emphasis feature. This is useful with longer distance appli-
cations or with high-loss interconnects. A resistor is connect-
ed to the PRE pin to ground and the value sets the amount of
additional output current that is driven. If the following logic bit
is the same logic state, the “additional” current is turned off
for the following bit. With this scheme, ISI (jitter) is reduced
and also some power is saved.
Other FPD-Link II line drivers provide De-Emphasis. Similar
to Pre-Emphasis, this feature is adjustable via an external re-
sistor. A serial control bus provides another means to adjust
a programmable register setting. De-Emphasis reduces the
differential output swing after the initial data transition, thus
minimizing ISI.
Certain FPD-Link II line drivers also support a differential out-
put voltage magnitude select pin. This pin is typically set to
low for standard swings. But if a larger VOD is desired, the
pin allows for an increased swing setting by setting it High.
Cable equalization is provided by some FPD-Link II receivers.
This feature compensates for cable loss. Adjustment is made
via pin control or serial bus controlled registers.
NSID (root)
SER
DES
SER
DES
SER
SER
Function
TABLE 1. Select FPD-Link II SER and DES Device Comparison Table
FIGURE 3. 24-bit RGB FPD-Link II SERDES XGA Display Application
18-bit
18-bit
18-bit
18-bit
18-bit
24-bit
(bits per pixel)
Color Depth
3
3
3
3
3
N/A
3
Purpose I/O
General
EMI Mitigation Features
The differential LVDS style physical layer is used to help min-
imize the generation of EMI. Line driver transition times are
controlled to be balanced and centered. This is done to min-
imize any common-mode currents from the line driver. The
odd-mode (differential) signaling generates equal and oppo-
site currents in the pair which also help to lower overall
emissions. The serial link is terminated at both the source and
load ends to minimize any signal reflections. Certain parts
provide internal terminations to reduce external part count
and to also minimize the resulting stub lengths.
The Parallel Bus at the DES (receiver output) is also opti-
mized to reduce EMI. Edge rates are controlled, and on
certain DES devices an output drive strength control is pro-
vided. Most DES devices support PTO (progressive turn-on),
a feature that groups the data outputs into banks and offsets
the switching point in time to reduce simultaneous switching
and thus reduce supply noise. Other devices employ frequen-
cy spread PTO to dynamically alter the output switching se-
quence and further enhance the noise reduction of the wide
bus. Spread spectrum clock generation is provided by some
deserializers. This feature modulates the output clock and
data period to effectively spread the energy associated with
periodic output transitions and minimize emissions.
Current FPD-Link II SerDes Devices
Many variants of FPD-Link II SER and DES devices are cur-
rently available with more to follow.
LVCMOS
LVCMOS
LVCMOS
LVCMOS
FPD-Link (3D + C LVDS) 5 to 43
LVCMOS
Parallel Interface
5 to 35
5 to 35
5 to 43
5 to 43
5 to 65
30055803
PCLK (MHz)
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