CDB5451A Cirrus Logic Inc, CDB5451A Datasheet - Page 10

• Manufacturer Part Number: CDB5451A
• Description: EVAL BOARD CS5451A 6CH ADC
• Manufacturer: Cirrus Logic Inc

Specifications of CDB5451A

• Number Of Adc's: 6
• Number Of Bits: 6
• Data Interface: Serial
• Inputs Per Adc: 2 Differential
• Input Range: 1.6 Vpp
• Power (typ) @ Conditions: 27mW @ 3 V
• Voltage Supply Source: Analog and Digital, Dual ±
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: CS5451A
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 598-1009

When data is not being transferred SCLK is held low.
(see Figure 3.)
The framing signal (FSO) output is normally low. FSO
goes high, with a pulse width equal to one SCLK period,
when the instantaneous voltage and current data sam-
ples are about to be transmitted out of the serial inter-
face (after each A/D conversion cycle). SCLK is not
active during FSO high.
For 96 SCLK periods after FSO falls, SCLK is active and
SDO provides valid output. Six channels of 16-bit data
are output, MSB first. Figure 4 illustrates how the volt-
age and current measurements are output for the three
phases. SCLK will then be held low until the next sam-
ple period.
4.5
A hardware reset is initiated when the RESET pin is
forced low with a minimum pulse width of 50 ns. When
10
SCLK
FSO
SDO
SCLK
FSO
SDO
System Initialization
[ Low ]
Each data segment
is 16 bits long.
Channel 1 V
Channel 1 I
15
14
13
Channel 2 V
12
11
10
Channel 1 ( V )
9
8
7
96 SCLKs
6
5
Figure 4. Serial Port Data Transfer
4
Channel 2 I
3
2
1
0
15
Figure 3. One Data Frame
Channel 3 V
14
13 12 11 10 9 8
Channel 3 I
96 SCLKs
Channel 1 ( I )
7 6 5 4 3 2 1
RESET is activated, all internal registers are set to a de-
fault state.
Upon powering up, the RESET pin must be held low
(active) until after the power stabilizes.
4.6
The CS5451A is specified for operation with a +1.2 V
reference between the VREFIN and AGND pins. The
converter includes an internal 1.2 V reference that can
be used by connecting the VREFOUT pin to the VRE-
FIN pin of the device. The VREFIN can be used to con-
nect external filtering and/or references.
4.7
The low, stable analog power consumption and superior
supply rejection of the CS5451A allow for the use of a
simple charge-pump negative supply generator. The
use of a negative supply alleviates the need for level
0 15 14
Voltage Reference
Power Supply
Ch. 2 ( V ) Ch. 2 ( I ) Ch. 3 ( V ) Ch. 3 ( I )
. . .
. . .
. . .
...
...
...
. . .
3
2
1
0
CS5451A
[ Low ]
DS635F3
. . .
. . .
. . .