CDB5451A Cirrus Logic Inc, CDB5451A Datasheet - Page 5

• Manufacturer Part Number: CDB5451A
• Description: EVAL BOARD CS5451A 6CH ADC
• Manufacturer: Cirrus Logic Inc

Specifications of CDB5451A

• Number Of Adc's: 6
• Number Of Bits: 6
• Data Interface: Serial
• Inputs Per Adc: 2 Differential
• Input Range: 1.6 Vpp
• Power (typ) @ Conditions: 27mW @ 3 V
• Voltage Supply Source: Analog and Digital, Dual ±
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: CS5451A
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 598-1009

ANALOG CHARACTERISTICS
Notes:
DIGITAL CHARACTERISTICS
•
•
•
•
Notes:
DS635F3
Power Supplies
Power Supply Currents
Typical VA+ = VD+ = +3 V; VA- = -2 V
Power Consumption
(Note 2)
Power Supply Rejection
50, 60 Hz (Note 3)
50, 60 Hz (Note 3)
Master Clock Characteristics
Master Clock Frequency
Master Clock Duty Cycle
Filter Characteristics
High Rate Filter Output Word Rate
Input/Output Characteristics
High-Level Input Voltage
Low-Level Input Voltage
High-Level Output Voltage
Low-Level Output Voltage
Input Leakage Current
3-State Leakage Current
Digital Output Pin Capacitance
Min/Max characteristics and specifications are guaranteed over all Operating Conditions.
Typical characteristics and specifications are measured at nominal supply voltages and TA = 25 °C.
VA+ = VD+ = 3V ±10%; VA- = -2 V ±10%; AGND = DGND = 0 V. All voltages with respect to 0 V.
XIN = 4.096 MHz
1. Specifications for Gain = 20 apply only to Current Channels. Voltage Channels are fixed to Gain = 1
2. All outputs unloaded. All inputs CMOS level.
3. Definition for PSRR: VREFIN tied to VREFOUT, VA+ = VD+ = 3 V, AGND = DGND = 0 V, VA- = -2 V (using charge-
4. All measurements performed under static conditions.
5. For OWRS and GAIN pins, input leakage current is 30 µA (Max).
pump circuit with CPD). In addition, a 106.07 mV rms (60 Hz) sinewave is imposed onto the VA+ and VD+ pins.
The “+” and “-” input pins of both input channels are shorted to VA-. 2048 instantaneous digital output data words
are collected for the channel under test. The rms value of the digital sinusoidal output signal is calculated, and this
rms value is converted into the rms value of the sinusoidal voltage (measured in mV) that would need to be applied
at the channel’s inputs, in order to cause the same digital sinusoidal output. This voltage is then defined as Veq.
PSRR is then (in dB):
Parameter
Parameter
(See Note 4)
(continued)
PSRR
Voltage Channel
Current Channel
I
out
I
out
I
D+
=
OWRS = 0
OWRS = 1
= -5.0 mA
I
= 5.0 mA
Without CPD
D+
without CPD
20
(Note 5)
With CPD
with CPD
⋅
log
(DC)
I
A+



Symbol
OWR
OWR
106.07
----------------- -
V
C
V
XIN
V
V
I
I
V eq
OZ
OH
OL
out
in
IH
IL
Symbol
PSCA
PSCD
PSCD
PSRR
PSRR
PSRR
PC
PC



(VD+) - 1.0
0.6 VD+
Min
0.0
40
3
-
-
-
-
-
-
Min
50
50
60
-
-
-
-
-
XIN/2048
XIN/1024
4.096
Typ
±1
Typ
4.0
5.0
1.0
9
-
-
-
-
-
-
27
23
65
90
-
CS5451A
Max
Max
VD+
5.3
6.3
1.5
±10
±10
35
31
0.8
0.4
60
-
-
-
5
-
-
-
-
Unit
mW
mW
MHz
mA
mA
mA
Unit
dB
dB
dB
Hz
Hz
µA
µA
pF
%
V
V
V
V
5