ADC14V155HFEB/NOPB National Semiconductor, ADC14V155HFEB/NOPB Datasheet - Page 18

• Manufacturer Part Number: ADC14V155HFEB/NOPB
• Description: BOARD EVAL ADC12V155HF >150MHZ
• Manufacturer: National Semiconductor
• Series: PowerWise®r

Specifications of ADC14V155HFEB/NOPB

• Number Of Adc's: 1
• Number Of Bits: 14
• Sampling Rate (per Second): 155M
• Data Interface: Parallel
• Inputs Per Adc: 1 Differential
• Power (typ) @ Conditions: 951mW @ 155MSPS
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: ADC14V155
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ADC14V155HFEB

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2.3 Control Inputs
2.3.1 Power-Down & Sleep (PD/Sleep)
The power-down and sleep modes can be enabled through
this three-state input pin. Table 2 shows how to utilize these
options.
The power-down and sleep modes allows the user to con-
serve power when the converter is not being used. In the
power-down state all bias currents of the analog circuitry, ex-
cluding the reference are shut down which reduces the power
consumption to 15 mW with no clock running. In sleep mode
some additional buffer circuitry is left on to allow an even
faster wake time; power consumption in the sleep mode is 50
mW with no clock running. In both of these modes the output
data pins are undefined and the data in the pipeline is cor-
rupted.
The Exit Cycle time for both the sleep and power-down mode
is determined by the value of the capacitors on the V
and V
capacitors lose their charge when the ADC is not operating
and must be recharged by on-chip circuitry before conver-
sions can be accurate. For power-down mode the Exit Cycle
time is about 3 ms with the recommended component values.
The Exit Cycle time is faster for sleep mode. Smaller capacitor
values allow slightly faster recovery from the power down and
sleep mode, but can result in a reduction in SNR, SINAD and
ENOB performance.
2.3.2 Clock Mode Select/Data Format (CLK_SEL/DF)
Single-ended versus differential clock mode and output data
format are selectable using this quad-state function pin. Table
3 shows how to select between the clock modes and the out-
put data formats.
3.0 CLOCK INPUTS
The CLK+ and CLK− signals control the timing of the sampling
process. The CLK_SEL/DF pin (pin 8) allows the user to con-
TABLE 3. Clock Mode and Data Format Selection Table
Input Voltage
CLK_SEL/DF
RN
TABLE 2. Power Down/Sleep Selection Table
(2/3) * V
(1/3) * V
AGND
reference bypass pins (pins 43, 44 and 45). These
V
A
PD Input Voltage
A
A
AGND
V
V
A
A
/2
Single-Ended
Single-Ended
Clock Mode
Differential
Differential
Power State
Power-down
Sleep
On
2's Complement
2's Complement
Offset Binary
Offset Binary
Output Data
Format
RP
, V
RM
18
figure the ADC for either differential or single-ended clock
mode (see Section 3.3). In differential clock mode, the two
clock signals should be exactly 180° out of phase from each
other and of the same amplitude. In the single-ended clock
mode, the clock signal should be routed to the CLK+ input and
the CLK− input should be tied to AGND in combination with
the correct setting from Table 3.
To achieve the optimum noise performance, the clock inputs
should be driven with a stable, low jitter clock signal in the
range indicated in the Electrical Table. The clock input signal
should also have a short transition region. This can be
achieved by passing a low-jitter sinusoidal clock source
through a high speed buffer gate. This configuration is shown
in Figure 4. The trace carrying the clock signal should be as
short as possible and should not cross any other signal line,
analog or digital, not even at 90°. Figure 4 shows the recom-
mended clock input circuit.
The clock signal also drives an internal state machine. If the
clock is interrupted, or its frequency is too low, the charge on
the internal capacitors can dissipate to the point where the
accuracy of the output data will degrade. This is what limits
the minimum sample rate.
The clock line should be terminated at its source in the char-
acteristic impedance of that line. Take care to maintain a
constant clock line impedance throughout the length of the
line. Refer to Application Note AN-905 for information on set-
ting characteristic impedance.
It is highly desirable that the the source driving the ADC clock
pins only drive that pin. However, if that source is used to drive
other devices, then each driven pin should be AC terminated
with a series RC to ground, such that the resistor value is
equal to the characteristic impedance of the clock line and the
capacitor value is
where t
"L" is the line length and Z
of the clock line. This termination should be as close as pos-
sible to the ADC clock pin but beyond it as seen from the clock
source. Typical t
board material. The units of "L" and t
(inches or centimeters).
The duty cycle of the clock signal can affect the performance
of the A/D Converter. Because achieving a precise duty cycle
is difficult, the ADC14V155 has a Duty Cycle Stabilizer. It is
designed to maintain performance over a clock duty cycle
range of 30% to 70%.
PD
is the signal propagation rate down the clock line,
PD
is about 150 ps/inch (60 ps/cm) on FR-4
O
is the characteristic impedance
PD
should be the same