ADP2114-2PH-EVALZ Analog Devices Inc, ADP2114-2PH-EVALZ Datasheet
ADP2114-2PH-EVALZ
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ADP2114-2PH-EVALZ Summary of contents
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... SYNC 22kΩ 10nF 1.2nF The ADP2114 input voltage range is from 2. 5.5 V, and it converts to fixed outputs of 0.8 V, 1.2 V, 1.5 V, 1 3.3 V that can be set independently for each channel using external resistors. Using a resistor divider also possible to set the output voltage as low as 0.6 V. The ADP2114 operates over the − ...
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... ADP2114 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Typical Application Circuit ............................................................. 1 Revision History ............................................................................... 2 Specifications ..................................................................................... 3 Absolute Maximum Ratings ............................................................ 5 ESD Caution .................................................................................. 5 Pin Configuration and Function Descriptions ............................. 6 Typical Performance Characteristics ............................................. 8 Supply Current ............................................................................ 13 Load Transient Response ........................................................... 14 Bode Plots .................................................................................... 19 Simplified Block Diagram ............................................................. 20 Theory of Operation ...................................................................... 21 Control Architecture .................................................................. 21 Undervoltage Lockout (UVLO) ............................................... 21 Enable/Disable Control ...
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... FB2 FB1 1 550 1.12 2.36 0.65 0.70 0.597 0.600 0.594 0.600 −1.0 −1.5 0.05 0.03 255 300 510 600 1020 1200 400 800 1600 100 ADP2114 Max Unit 5 2.5 mA 2 μ μA μA 0.603 V 0.606 V +1 ...
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... ADP2114 Parameter SYNC Pin Capacitance to GND SYNC Input Logic Low SYNC Input Logic High Phase Shift Between Channels CLKOUT Frequency CLKOUT Positive Pulse Time CLKOUT Rise or Fall Time CURRENT LIMIT Peak Output Current Limit, Channel 1 Peak Output Current Limit, Channel 2 Current Sense Amplifier Gain ...
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... Absolute maximum ratings apply individually only, not in −0.3V to +3.6V combination. −0 (VDD + 0.3 V) ±0.3 V ESD CAUTION ±0.3 V 34°C/W −40°C to +125°C −65°C to +150°C 260°C Rev Page ADP2114 ...
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... VDD Power Supply Input. The power source for the ADP2114 internal circuitry. Connect VDD and VINx with a 10 Ω resistor as close as possible to the ADP2114. Bypass VDD to GND with a 1 μF or greater capacitor. 9 FB2 Feedback Voltage Input for Channel 2. For the fixed output voltage option, connect FB2 to V adjustable output voltage option, connect this pin to a resistor divider between V voltage for the adjustable output voltage option is 0 ...
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... V configurations, connect FB1 to FB2 and then connect them to V EPAD (EP) Exposed Thermal Pad. Connect to the signal/analog ground plane. . OUT Rev Page ADP2114 . See Table 4 OUT1 . For the OUT1 and GND. With multiphase OUT1 ...
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... ADP2114 TYPICAL PERFORMANCE CHARACTERISTICS 100 OUT V OUT 65 V OUT V OUT 60 10 100 LOAD CURRENT (mA) Figure 4. Channel 1 Efficiency vs. Load 3.3 V, Inductor Cooper Bussmann DR1050-8R2-R, 8.2 μH, 15 mΩ; OUT V = 1.8 V, Inductor TOKO FDV0620-4R7M, 4.7 μH, 53 mΩ OUT 100 OUT V OUT 65 V OUT ...
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... V (V) IN 1.00 0.75 0.50 0. 5.5V, NO LOAD 2.75V; 2A LOAD IN –50 – TEMPERATURE (°C) Figure 13. Output Voltage vs. Temperature, Channel 1.5 V and f = 600 kHz OUT SW ADP2114 2000 = 25°C A 5.0 5.5 = 600 kHz SW 100 125 ...
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... ADP2114 250 f = 300kHz 600kHz 225 1.2MHz SW 200 175 150 125 100 75 50 2.5 3.0 3.5 4.0 V (V) IN Figure 14. Minimum On-Time, Open Loop, Includes Dead Time 350 f = 300kHz SW 330 f = 600kHz 1.2MHz 310 SW 290 270 250 230 210 190 170 150 2.5 3.0 3 ...
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... SW 1300 1280 1260 1240 1220 1200 1180 1160 1140 1120 1100 5.0 5.5 –50 Figure 25. Switching Frequency vs. Temperature 1.2 MHz SW Rev Page ADP2114 ENABLE 5.5V IN ENABLE 2.75V IN DISABLE 5.5V IN DISABLE 2.75V IN – 100 TEMPERATURE (°C) V RISING DD ...
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... ADP2114 120 OVERVOLTAGE; V RISING OUT 115 110 OVERVOLTAGE; V FALLING OUT 105 100 95 UNDERVOLTAGE; V RISING OUT 90 UNDERVOLTAGE, V FALLING OUT 85 80 –50 – TEMPERATURE (°C) Figure 26. PGOOD Threshold vs. Temperature 5. 2.75V –50 – TEMPERATURE (°C) Figure 27. Shutdown Current vs. Temperature 5. 2.75V –50 – TEMPERATURE (°C) Figure 28 ...
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... FORCED PWM DD 4.5 4 2.75V, FORCED PWM DD 3.5 3 5.5V PULSE SKIP DD 2 2.75V, PULSE SKIP DD 2.0 1.5 1.0 –50 – TEMPERATURE (°C) Figure 34. V Supply Current vs. Temperature, DD Channel 1.5 V, Channel 0 OUT OUT ADP2114 5.0 5.5 = 1.2 MHz SW 100 125 = 1.2 MHz SW ...
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... ADP2114 LOAD TRANSIENT RESPONSE V OUT 2 I OUT CH1 5.0V CH2 50mV M200µs 50MS/s CH4 2.0A 200ns/pt Figure 35. Channel 3.3V OUT (See Table 12 for the Circuit Details) V OUT 2 I OUT CH3 5.0V CH2 50mV M200µs 50MS/s CH4 2.0A 200ns/pt Figure 36. Channel ...
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... CH3 1.0V Figure 45. 3 Line Transient OUT 4.84V CH1 2.0V CH3 1.0V Figure 46 3.3 V Line Transient, V Rev Page ADP2114 CH2 10mV M400µs A CH3 3.50V = 1.5 V, Load = 1 A OUT f = 1.2 MHz, Forced PWM SW CH2 10mV M400µs A CH3 4.82V = 0.6 V, Load = 1 A ...
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... ADP2114 V OUT CH1 2.0V CH2 10mV M400µs CH3 1.0V Figure 47. 3 Line Transient, V OUT f = 600 kHz, Forced PWM SW V OUT CH1 2.0V CH2 10mV M400µs CH3 1.0V Figure 48 3.3 V Line Transient, V OUT f = 600 kHz, Forced PWM OUT INDUCTOR CURRENT ...
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... Figure 56. Hiccup Mode 1.12V CH3 5.0V = 600 kHz 1.12V CH1 5.0V CH3 5.0V Figure 58. External Synchronization 600 kHz Rev Page ADP2114 INDUCTOR CURRENT V OUT SW CH2 1.0V M2.0ms A CH4 1.72V CH4 2.0A = 600 kHz, 6.8 ms Hiccup Cycle SW INDUCTOR CURRENT V OUT SW CH2 1.0V M2 ...
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... CH4 5.0V Figure 59. Internal Clock Out 600 kHz CHANNEL CHANNEL CHANNEL 4 SW CH1 2.0V CH2 2.0V M1.0µs CH3 2.0V CH4 2.0V Figure 60. 4-Channel Operation, Two ADP2114s, One Synchronizes Another, 90° Phase-Shifted Switch Nodes CH3 3.0V = 1.2 MHz CLKOUT CHANNEL CH1 2 ...
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... MHz, Crossover Frequency ( kHz; Phase Margin 53° (See Table 12 for the Circuit Details Rev Page 150 120 90 60 PHASE 30 0 –30 –60 –90 –120 –150 M2 120 96 72 PHASE –24 –48 –72 –96 –120 M2 1M ADP2114 ...
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... ADP2114 SIMPLIFIED BLOCK DIAGRAM SCFG FREQ OSC SYNC/CLKOUT CURRENT LIMIT/ OPCFG CONFIGURATION EN1 COMP1 V1SET FB1 SS1 6µ EN2 COMP2 V2SET FB2 SS2 6µ GND DD UVLO UVLO OSC_CH1 0.7V PHASE SHIFT OSC_CH2 VFB1 CLIM_CH1 CLIM_CH2 0.5V PULSE SKIP ENABLE CONTROL UVLO ...
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... SOFT START The ADP2114 soft start feature allows the output voltage to ramp controlled manner, eliminating output voltage overshoot during startup. Soft start begins after the undervoltage lockout threshold is exceeded and the enable pin, EN1 (EN2), is pulled high above 2 ...
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... A CH1 2.4V mode, when the output voltage dips below regulation, the ADP2114 enters PWM mode for a few oscillator cycles to increase the output voltage back to regulation. During the wait time between bursts, both power switches are off, and the output capacitor supplies all load current. Because the output ...
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... SYNC pin or an output CLKOUT pin through the SCFG pin, as shown in Table 6. Through the input SYNC pin, the ADP2114 can be synchronized to an external clock such that the two channels switch at half the external clock, 180° out of phase. Through the output CLKOUT pin, the ADP2114 provides an output clock that is twice the switching frequency of the channels and 90° ...
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... GND. For the adjustable output voltage range of 1 3.3 V, tie V1SET (V2SET) to VDD (see Table 4). The adjustable output voltage of ADP2114 is externally set by a resistive voltage divider from the output voltage to the feedback pin (see Figure 71). The ratio of the resistive voltage divider sets the output voltage, while the absolute value of those resistors sets the divider string current ...
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... SETTING THE OSCILLATOR FREQUENCY The ADP2114 channels can be set to operate in one of the three preset switching frequencies: 300 kHz, 600 kHz, or 1.2 MHz. For 300 kHz operation, connect the FREQ pin to GND. For 600 kHz or 1.2 MHz operation, connect a resistor between the FREQ pin and GND, as shown in Table 5 ...
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... ADP2114 OPERATION MODE CONFIGURATION The dual-channel ADP2114 can be configured to one of the four modes of operation by connecting the OPCFG pin as shown in Table 7. This configuration sets the current limit for each channel and enables or disables the transition to pulse skip mode at light loads. In the dual-phase configuration, the outputs of the two channels ...
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... ESR that is low enough to mitigate the input voltage ripple. For the ADP2114, place a 22 μF, 6.3 V, X5R ceramic capacitor close to the VINx pin for each channel. X5R or X7R dielectrics are recommended with a voltage rating of 6 ...
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... ADP2114 The ADP2114 can be configured in either A/1 A current limit configuration and, therefore, the current limit thresholds for the two channels are different in each setting. The inductor chosen for each channel must have at least the peak output current limit of the IC in each case for robust operation during short-circuit conditions ...
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... CROSS OUT OUT ⎜ ⎜ ⎟ COMP G G ⎝ V ⎝ ⎠ REF 1 = × × × COMP 2 π ZERO COMP (as shown in Figure 77) forms a pole with the the feedback loop to ensure COMP , if used, is typically set COMP ADP2114 (16) REF (17) ⎞ ⎟ (18) ⎟ ⎠ (19) ...
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... ADP2114 DESIGN EXAMPLE The external component selection procedure from the Control Loop Compensation section is used for this design example. Table 9. 2-Channel Step-Down DC-to-DC Converter Requirements Parameter Specification Input Voltage, V 5.0 V ±10% IN Channel OUT1 OUT ripple (p-p) Channel OUT2 OUT ...
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... C ΔI ⎜ × OUT_MIN OUT_STEP ⎝ f ΔV SW DROOP = 0.582 600 kHz (1% of 1.8 V) RIPPLE = 1 A OUT_STEP = 0.09 V (5% of 1.8 V) DROOP = 7.7 μF, whereas the transient load based OUT ADP2114 = 0.3 × ⎞ ⎟ ⎟ ⎠ ), and RIPPLE = 55 μF. To OUT ...
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... Tie OPCFG to GND for 2 A/2 A maximum output current operation and to enable pulse skip mode at light load conditions (see Table 7). A schematic of the ADP2114 as configured in the design example described in this section is shown in Figure 79. Table 12 provides the recommended inductor, output capacitor, and compensation component values for a set of popular input = 1100 pF ...
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... SYNC/CLKOUT 1000pF 22nF 27kΩ 4.7kΩ IN 1.2MHz Figure 80. Application Circuit for a Single 4 A Output Rev Page 100kΩ 22µF PGOOD1 3.3µ 3.3V, 2A OUT1 47µF 47kΩ 27kΩ 10nF 1000pF 10µF PGOOD V = 1.2V, 4A OUT 47µF 22µF ADP2114 ...
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... Figure 81. Application Circuit for 3 A/1 A Outputs 10Ω 1µF 100kΩ EN2 EN1 VIN4 VIN1 22µF VIN2 VIN5 VIN3 VIN6 PGOOD1 PGOOD2 SW1 = 1.4V, 2A SW3 ADP2114 SW2 1µH SW4 PGND1 PGND3 PGND2 PGND4 FB1 FB2 V1SET V2SET 82kΩ SYNC/CLKOUT COMP1 SYNC COMP2 SS1 SS2 22kΩ ...
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... Transition losses occur because the P-channel power MOSFET cannot be turned on or off instantaneously. The amount of transition loss is calculated by P (21) where t switching node, SW. In the ADP2114, the rise and fall times of the switching node are in the order of 5 ns. The power dissipated by the regulator increases the die junction . temperature ...
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... L and C back to the power ground plane as OUT short as possible this, ensure that the PGNDx pin of the ADP2114 is tied to the PGND plane as close as possible to the input and output capacitors (see Figure 84). • Connect the ADP2114 exposed pad to a large copper plane to maximize its power dissipation capability ...
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... OUTLINE DIMENSIONS PIN 1 INDICATOR 12° MAX 1.00 0.85 0.80 SEATING PLANE ORDERING GUIDE Model Temperature Range 2 ADP2114ACPZ-R7 −40°C to +85°C 2 ADP2114-2PH-EVALZ 2 ADP2114-EVALZ 1 Operating junction temperature is −40°C to +125° RoHS Compliant Part. 5.00 BSC SQ 0.60 MAX 24 0.50 BSC TOP 4.75 VIEW BSC SQ 0 ...
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... ADP2114 NOTES Rev Page ...
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... NOTES Rev Page ADP2114 ...
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... ADP2114 NOTES ©2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08143-0-7/09(0) Rev Page ...