DK86065-2 Fujitsu Semiconductor America Inc, DK86065-2 Datasheet - Page 17

• Manufacturer Part Number: DK86065-2
• Description: KIT EVAL 16BIT DAC FOR MB86065
• Manufacturer: Fujitsu Semiconductor America Inc

Specifications of DK86065-2

• Number Of Dac's: 1
• Number Of Bits: 14
• Outputs And Type: 1, Differential
• Sampling Rate (per Second): 1G
• Data Interface: Serial
• Dac Type: Current
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: MB86065
• For Use With: 865-1111 - DAC DK FPGA ADAPTER BOARD865-1012 - KIT DEV DUAL 14BIT MB86064 SMA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 865-1011

September 2007 Version 1.01
FME/MS/DAC80S/DS/5344
MB86065 14-bit 1+GSa/s DAC
1.7
Pin X_RESET is the device reset pin. On the falling edge of X_RESET the device is reset and all
registers are set to their default values. After a reset most parts of the device are powered down. See
Table 12, DAC Core Register POWER DOWN. Power to each internal block may be individually
controlled through this register.
An example of a typical setting is:
• 0x0000B80
This assumes both the divided clock outputs and loop-clocks are to be enabled.
Copyright © 2004-2007 Fujitsu Microelectronics Europe GmbH
Disclaimer : The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before
POWER DOWN
Reset and Power Down
ordering.The information and circuit diagrams in this document are presented “as is”, no license is granted by implication or otherwise.
(bit)
The DAC control register bit, pdn_dac, must be set in conjunction with the DAC CONFIG
register bit to ensure the correct internal reference current is used. See section 1.3.
10
12
11
0
1
2
3
4
5
6
7
8
9
DAC enabled for LVDS data
Table 12: DAC Core Register: POWER DOWN [0x1C3]
pdn_ckandrefs
pdn_loopcks
pdn_outcks
pdn_indatb
pdn_indata
pdn_reg18
pdn_reg25
pdn_regck
pdn_reglo
pdn_odat
pdn_dac
Label
Low voltage (~1.1V) regulator control
0 = Enabled (default) , 1 = Powered down
1.8V clock regulator control
0 = Enabled (default) , 1 = Powered down
1.8V DAC regulator control
0 = Enabled (default) , 1 = Powered down
2.5V bandgap regulator control
0 = Enabled (default) , 1 = Powered down
DAC common circuit (clocks, references and bias) control
0 = All enabled (default) , 1 = All powered down
Divided output clocks
0 = Enabled (default) , 1 = Powered down
Loop clocks
0 = Enabled, 1 = Powered down (default)
Reserved
Set to ‘1’ (default)
TEST access via DAC output
0 = Enabled, 1 = Disabled (default)
Port B data input power down control
0 = Enabled, 1 = Powered down (default)
Port A data input power down control
0 = Enabled, 1 = Powered down (default)
Reserved
Set to ‘1’ (default)
DAC control
0 = Enabled, 1 = Powered down (default)
Function
Production
N.B. See note below
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