DK86065-2 Fujitsu Semiconductor America Inc, DK86065-2 Datasheet - Page 7

• Manufacturer Part Number: DK86065-2
• Description: KIT EVAL 16BIT DAC FOR MB86065
• Manufacturer: Fujitsu Semiconductor America Inc

Specifications of DK86065-2

• Number Of Dac's: 1
• Number Of Bits: 14
• Outputs And Type: 1, Differential
• Sampling Rate (per Second): 1G
• Data Interface: Serial
• Dac Type: Current
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: MB86065
• For Use With: 865-1111 - DAC DK FPGA ADAPTER BOARD865-1012 - KIT DEV DUAL 14BIT MB86064 SMA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 865-1011

September 2007 Version 1.01
FME/MS/DAC80S/DS/5344
MB86065 14-bit 1+GSa/s DAC
1.1.3 Waveform Memory Module Clock Programmable Delay
A programmable delay stage is provided in the clock path prior to being applied to the Waveform
Memory Module. This delay stage is programmed through register SYSTEM CLOCK DELAYS, bits
wmm_clk_dly. See Table 2.
1.1.4 Clock Outputs
Two clock outputs, CLK1_OUT and CLK2_OUT, are provided to enable synchronisation of data
generating devices to the DAC. The reference clock used by the Clock Output block can be disabled
if required. See Table 4.
The output frequency can be individually selected as the input clock divided-by-1, 2, 4 or 8.
Configuration is through register WMM CONFIG, bits clkout1_cfg and clkout2_cfg. See Table 5.
Copyright © 2004-2007 Fujitsu Microelectronics Europe GmbH
Disclaimer : The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before
SYSTEM MISC
wmm_clk_dly
inv_wmm_clk
ordering.The information and circuit diagrams in this document are presented “as is”, no license is granted by implication or otherwise.
Table 2: DAC Core Register: SYSTEM CLOCK DELAYS [0x1C1] (Part 1 of 4)
Label
Label
(bit)
0
Table 3: DAC Core Register: SYSTEM MISC [0x1C4] (Part 1 of 4)
Table 4: DAC Core Register: SYSTEM MISC [0x1C4] (Part 2 of 4)
15
en_ref_clk
0
0
1
:
:
Label
Reg Bits
14
Reg Bit
0
1
1
:
:
2
0
1
13
0
0
1
:
:
Reference clock control
0 = Enabled (default), 1 = Disabled
12
0
1
1
:
:
Minimum (default & recommended)
Required for 1+ GSa/s mode when using WMM data
Maximum
Default (* Recommended for normal operation *)
Required for 1+ GSa/s mode when using WMM data
Waveform Memory Module Clock Inversion
Waveform Memory Module Clock Delay
(0 - 1.5ns, 100ps steps)
Function
Production
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