MT9D131C12STCH ES Aptina LLC, MT9D131C12STCH ES Datasheet - Page 13

KIT HEAD BOARD FOR MT9D131

MT9D131C12STCH ES

Manufacturer Part Number
MT9D131C12STCH ES
Description
KIT HEAD BOARD FOR MT9D131
Manufacturer
Aptina LLC
Series
Micron®DigitalClarity®r

Specifications of MT9D131C12STCH ES

Sensor Type
CMOS Imaging, Color (RGB)
Sensing Range
2 Megapixel
Interface
USB
Sensitivity
15 fps
Voltage - Supply
2.5 V ~ 3.1 V
Embedded
No
Utilized Ic / Part
MT9D131
Silicon Manufacturer
Aptina Imaging
Application Sub Type
Image Sensor
Kit Application Type
Sensing - Image / Light
Silicon Core Number
MT9D131
Kit Contents
Image Sensor And Lens
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
557-1253
Q4051985
Figure 6:
Die Outline
Figure 7:
PDF: 09005aef824c90ce/Source: 09005aef824c90d6
MT9D131_LDS_2.fm - Rev. B 3/07 EN
Sensor Core Block Diagram
Optical Center Offset
Note:
The core of the sensor is an active-pixel array. The timing and control circuitry
sequences through the rows of the array, resetting and then reading each row. In the
time interval between resetting a row and reading that row, the pixels in that row inte-
grate incident light. The exposure is controlled by varying the time interval between
reset and readout. After a row is read, the data from the columns is sequenced through
an analog signal chain (providing offset correction and gain), and then through an ADC.
The output from the ADC is a 10-bit value for each pixel in the array. The pixel array con-
tains optically active and light-shielded “black” pixels. The black pixels are used to pro-
vide data for on-chip offset correction algorithms (black level control).
Active-Pixel Sensor
Figure not to scale.
1600H x 1200V
Analog Processing
(APS) Array
UXGA
Last Clear Pixel
(Col 1683, Row 1235)
MT9D131: 1/3.2-Inch 2-Mp SOC Digital Image Sensor
(167.84μm, 2.06μm)
Optical Center
8199.35μm
(bare die)
(0μm, 0μm)
Die Center
13
Timing and Control
Control Register
ADC
First Clear Pixel
(Col 52, Row 20)
Micron Technology, Inc., reserves the right to change products or specifications without notice.
PLL
Signals
Serial
Data
Sync
Architecture Overview
Out
I/O
©2006 Micron Technology, Inc. All rights reserved.
Preliminary

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