HW-V5-PCIE2-UNI-G Xilinx Inc, HW-V5-PCIE2-UNI-G Datasheet - Page 58

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HW-V5-PCIE2-UNI-G

Manufacturer Part Number
HW-V5-PCIE2-UNI-G
Description
KIT DEV PCIEXPRESS GTX VIRTEX5
Manufacturer
Xilinx Inc
Series
Virtex™ -5r
Type
FPGAr

Specifications of HW-V5-PCIE2-UNI-G

Contents
Board, CD
For Use With/related Products
Virtex™-5 FPGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Part Number:
HW-V5-PCIE2-UNI-G
Manufacturer:
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0
Table 77: Operating Frequency Ranges for DCM in Maximum Range (MR) Mode
DS202 (v5.3) May 5, 2010
Product Specification
Notes:
1.
2.
3.
4.
Outputs Clocks (Low Frequency Mode)
F
F
F
F
F
F
F
F
Input Clocks (Low Frequency Mode)
F
F
F
F
F
F
1XMRMIN
1XMRMAX
2XMRMIN
2XMRMAX
DLLMRMIN
DLLMRMAX
FXMRMIN
FXMRMAX
CLKINDLLMRMIN
CLKINDLLMRMAX
CLKINFXMRMIN
CLKINFXMRMAX
PSCLKMRMIN
PSCLKMRMAX
DLL Outputs are used in these instances to describe the outputs: CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV.
DFS Outputs are used in these instances to describe the outputs: CLKFX and CLKFX180.
When using the DCMs CLKIN_DIVIDE_BY_2 attribute these values should be doubled. Other resources can limit the maximum input
frequency.
When using a CLKIN frequency > 400 MHz and the DCMs CLKIN_DIVIDE_BY_2 attribute, the CLKIN duty cycle must be within ±5% (45/55
to 55/45).
Symbol
CLK0, CLK90, CLK180, CLK270
CLK2X, CLK2X180
CLKDV
CLKFX, CLKFX180
CLKIN (using DLL outputs)
CLKIN (using DFS outputs only)
PSCLK
www.xilinx.com
Description
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
(1, 3, 4)
(2, 3, 4)
300.00
19.00
32.00
38.00
64.00
21.34
19.00
40.00
19.00
32.00
40.00
1.19
1.00
1.00
-3
Speed Grade
270.00
38.00
19.00
19.00
32.00
64.00
21.34
40.00
19.00
32.00
40.00
1.19
1.00
1.00
-2
240.00
19.00
32.00
38.00
64.00
21.34
19.00
40.00
19.00
32.00
40.00
1.19
1.00
1.00
-1
Units
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
KHz
58

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