HW-V5-ML550-UNI-G Xilinx Inc, HW-V5-ML550-UNI-G Datasheet - Page 34

• Manufacturer Part Number: HW-V5-ML550-UNI-G
• Description: EVALUATION PLATFORM VIRTEX-5
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXTr
• Type: FPGAr

Specifications of HW-V5-ML550-UNI-G

• Contents: Development Platform, Power Supply, Loopback Board, CompactFlash Card, software and documentation
• Silicon Manufacturer: Xilinx
• Features: 64M X 8 DDR SDRAM Memory, Six Samtec LVDS Connectors
• Kit Contents: Board, Cable, PSU, CD, Docs
• Silicon Family Name: Virtex-5
• Silicon Core Number: XC5VLX50T-FFG1136
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: Virtex™-5 LXT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Chapter 3: Hardware Description
ML550 System Monitor and Power Monitor Support
Table 3-13: ML550 System Monitor Connections
34
System Monitor
Input Channel
VAUXN[10]
VAUXN[12]
VAUXN[13]
VAUXN[11]
VAUXP[10]
VAUXP[11]
VAUXP[12]
VAUXP[13]
VAUXN[9]
VAUXP[9]
FPGA
Pin#
N32
U31
U32
U33
R34
T34
R32
R33
T33
P32
The Virtex-5 FPGA System Monitor block diagram is shown in
The ML550 board hosts several measurement circuits, external to the FPGA, which are
connected to the upper half of the input channels shown in the block diagram, namely the
inputs VAUXP/N[9:15] and VP/VN). VAUXP/N[0:8] are not supported on the ML550 as
these dual-purpose FPGA pins are used for other functions.
Detailed information concerning the System Monitor block is contained in UG192,
available at the following link:
The ML550 system monitor support circuitry is connected to the XC5VLX50T FFG-1136 as
shown in
V
V
V
V
CCAUX
Internal Supplies
CCINT
REFN
REFP
http://www.xilinx.com/support/documentation/user_guides/ug192.pdf
Parameter Measured
Temperature
VAUXP[14]
VAUXN[14]
VAUXP[15]
VAUXN[15]
2.5V V
2.5V V
2.5V System (N)
1.0V V
VAUXN[0]
2.5V System (P)
1.0V V
VAUXP[0]
2.5V V
2.5V V
5V Power (N)
5V Power (P)
Table
Sensor
VN
VP
CCAUX
CCAUX
CCINT
CCINT
Supply Sensor
CCO
CCO
3-13.
Mux
(N)
(P)
°C
(N)
(P)
(N)
(P)
Figure 3-11: Virtex-5 FPGA System Monitor
www.xilinx.com
Mux
VCCAUX2V5_MON_SM10N
VCCAUX2V5_MON_SM10P
VCCO2V5_MON_SM11N
VCCO2V5_MON_SM11P
VCC2V5_MON_SM12N
VCC1V0_MON_SM13N
VCC2V5_MON_SM12P
VCC1V0_MON_SM13P
VCC5V_MON_SM9N
VCC5V_MON_SM9P
System Monitor
Signal Name
200 kSPS
10-Bits
ADC
ML550 Networking Interfaces Platform
STATUS ALARM
Status Registers
FPGA Interconnect
Control Logic
3Eh
3Fh
02h
00h
01h
03h
Register File Interface
R network
R network
R network
R network
R network
R network
R network
R network
R network
R network
Sensor
Circuit
Figure
UG202 (v1.4) April 18, 2008
CONTROL
CLOCK
and
3-11.
Control Registers
Reconfiguration
DRP
Port (DRP)
Dynamic
Schematic
40h
41h
42h
43h
7Eh
7Fh
UG202_3_11_041708
Sheet(s)
Controller
JTAG TAP
19, 34
19, 34
20, 34
20, 34
20, 34
20, 34
20, 34
20, 34
20, 34
20, 34
R