HW-V5-ML550-UNI-G Xilinx Inc, HW-V5-ML550-UNI-G Datasheet - Page 84

• Manufacturer Part Number: HW-V5-ML550-UNI-G
• Description: EVALUATION PLATFORM VIRTEX-5
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXTr
• Type: FPGAr

Specifications of HW-V5-ML550-UNI-G

• Contents: Development Platform, Power Supply, Loopback Board, CompactFlash Card, software and documentation
• Silicon Manufacturer: Xilinx
• Features: 64M X 8 DDR SDRAM Memory, Six Samtec LVDS Connectors
• Kit Contents: Board, Cable, PSU, CD, Docs
• Silicon Family Name: Virtex-5
• Silicon Core Number: XC5VLX50T-FFG1136
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: Virtex™-5 LXT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Appendix C: LCD Interface
84
DataIn
Ena
Clk
Rst
8
Counter B
Clk
Position
Register
A state machine takes care of the processing order.
A minimum cycle time of 400 ns on the E signal used as a reference. The 200 MHz system
clock frequency is used as reference system clock. One E cycle uses at least 80 system clock
cycles when the design is running at 200 MHz. The E pulse is part of the state machine, and
the design only depends on the system clock. Timing is met as long as the system clock
does not exceed 200 MHz.
This design can be adapted easily to fit the MicroBlaze™ or PPC405 CoreConnect bus
system.
E
E
TC
DesRst
DesRst
DesRst
Display
Register
Load
Figure C-11: LCD Character Generator Controller
3
11
Count to 8.
Stop both counters at TC.
Send character position and
line to the LCD.
Load new value in counter A.
Switch to character ROM.
Enable counters.
Clk
Counter A
E
L
DesRst
www.xilinx.com
DesRst
11
Ena
We
Clk
DesRst
Ssr
DI
Addr
RAMB16_S9
Ena
Clk
Rst
Page
DO
State Machine
ML550 Networking Interfaces Platform
8
Clk
UG202 (v1.4) April 18, 2008
8
UG202_C_11_050906
RS
RW
E
0
1
LUT-ROM
Display
Initialization
8
Data
R