ATICE50 Atmel, ATICE50 Datasheet - Page 64

• Manufacturer Part Number: ATICE50
• Description: EMULATOR IN CIRCUIT MEGAAVR
• Manufacturer: Atmel

Specifications of ATICE50

• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

2523A–AVR–11/02
Trace
Table 7-3. Branch Instructions (Continued)
7-10
Instruction
INSTA
[0..15]
SBRC
SBRS
SBIC
SBIS
BRBS
BRBC
BREQ
PMem Addr
[PC[A0..22]
1. Address of instruction
1. Address of instruction
2. Address of skipped
instruction
1. Address of instruction
2. Address of skipped
instruction, first word
3. Address of skipped
instruction, second word
1. Address of instruction
1. Address of instruction
2. Address of skipped
instruction
1. Address of instruction
2. Address of skipped
instruction, first word
3. Address of skipped
instruction, second word
1. Address of instruction
1. Address of instruction
2. Address of skipped
instruction
1. Address of instruction
2. Address of skipped
instruction, first word
3. Address of skipped
instruction, second word
1. Address of instruction
1. Address of instruction
2. Address of skipped
instruction
1. Address of instruction
2. Address of skipped
instruction, first word
3. Address of skipped
instruction, second word
1. Address of instruction
1. Address of instruction
2. N/A
1. Address of instruction
1. Address of instruction
2. N/A
1. Address of instruction
1. Address of instruction
2. N/A
(5)
(5)
(5)
(3)
(3)
(3)
(3)
(4)
(4)
(4)
(4)
(2)
(3)
(4)
(2)
(3)
(4)
(2)
(3)
(4)
(2)
(3)
(4)
(6)
(5)
(6)
(5)
(6)
(5)
(4)
(4)
(4)
(4)
Reg.Val
RegFileL
[0..7]
1. N/A
1. N/A
2. N/A
1. N/A
2. N/A
3. N/A
1. N/A
1. N/A
2. N/A
1. N/A
2. N/A
3. N/A
1. N/A
1. N/A
2. N/A
1. N/A
2. N/A
3. N/A
1. N/A
1. N/A
2. N/A
1. N/A
2. N/A
3. N/A
1. N/A
1. N/A
2. N/A
1. N/A
1. N/A
2. N/A
1. N/A
1. N/A
2. N/A
(2)
(3)
(3)
(4)
(4)
(4)
(2)
(3)
(3)
(4)
(4)
(4)
(2)
(3)
(3)
(4)
(4)
(4)
(2)
(3)
(3)
(4)
(4)
(4)
(6)
(5)
(5)
(6)
(5)
(5)
(6)
(5)
(5)
Dat.Addr
RAM_EEADDR
[0..22]
1. N/A
1. N/A
2. N/A
1. N/A
2. N/A
3. N/A
1. N/A
1. N/A
2. N/A
1. N/A
2. N/A
3. N/A
1. 5 LSB give I/O address (A)
1. 5 LSB give I/O address (A)
2. N/A
1. 5 LSB give I/O address (A)
2. N/A
3. N/A
1. 5 LSB give I/O address (A)
1. 5 LSB give I/O address (A)
2. N/A
1. 5 LSB give I/O address (A)
2. N/A
3. N/A
1. N/A
1. N/A
2. N/A
1. N/A
1. N/A
2. N/A
1. N/A
1. N/A
2. N/A
(2)
(3)
(3)
(4)
(4)
(4)
(2)
(3)
(3)
(4)
(4)
(4)
(3)
(4)
(4)
(3)
(4)
(4)
(6)
(5)
(5)
(6)
(5)
(5)
(6)
(5)
(5)
(2)
(3)
(4)
(2)
(3)
(4)
Dat.Val
1. N/A
1. N/A
2. N/A
1. N/A
2. N/A
3. N/A
1. N/A
1. N/A
2. N/A
1. N/A
2. N/A
3. N/A
1. N/A
1. N/A
2. N/A
1. N/A
2. N/A
3. N/A
1. N/A
1. N/A
2. N/A
1. N/A
2. N/A
3. N/A
1. N/A
1. N/A
2. N/A
1. N/A
1. N/A
2. N/A
1. N/A
1. N/A
2. N/A
(2)
(3)
(3)
(4)
(4)
(4)
(2)
(3)
(3)
(4)
(4)
(4)
(2)
(3)
(3)
(4)
(4)
(4)
(3)
(3)
(4)
(4)
(4)
(6)
(5)
(5)
(6)
(5)
(5)
(6)
(5)
(5)
(2)
ICE50 User Guide
Status
Register
N/A
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N/A
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