MPC8360E-MDS-PBE Freescale Semiconductor, MPC8360E-MDS-PBE Datasheet
MPC8360E-MDS-PBE
Specifications of MPC8360E-MDS-PBE
Related parts for MPC8360E-MDS-PBE
MPC8360E-MDS-PBE Summary of contents
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... Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2. Application Examples . . . . . . . . . . . . . . . . . . . . . . . . . 3 2.1. DSLAM Line Card . . . . . . . . . . . . . . . . . . . . . . . 3 2.2. Node B Network Interface Card . . . . . . . . . . . . . 4 2.3. SME Router . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3. Architecture Overview . . . . . . . . . . . . . . . . . . . . . . . . 6 3.1. MPC8360E Features . . . . . . . . . . . . . . . . . . . . . . 6 3.2. QUICC Engine . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.3. Security Engine . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.4. Dual DDR Memory Controllers . . . . . . . . . . . . . 9 3.5. PCI Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.6. Programmable Interrupt Controller (PIC ...
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... Overview the MPC8360E. The QUICC Engine contains several peripheral controllers and integrates two 32-bit RISC controllers. Each RISC controller can control multiple peripherals and they work together to provide increased aggregated system bandwidth for higher throughput applications. Protocol support is provided by the main workhorses of the device—the unified communication controllers (UCCs) and multi-channel communication controller (MCC) ...
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... This helps ensure that a low-cost system solution can be quickly developed and will offer flexibility to accommodate new standards and evolving system requirements. 2 Application Examples The internal features of the MPC8360E make it suitable for a wide variety of network communication applications as described in this section. 2.1 ...
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... DSLAM line-card via the DSL PHYs and the integrated UTOPIA interface on the MPC8360E. In this type of application, the MPC8360E makes use of its internal interworking features to offload the e300 CPU. Here, ATM-ATM interworking would be used to transfer data from the ATM based DSL subscriber inputs, through the cores within the QUICC Engine and out through the other ATM UTOPIA on the uplink port ...
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... UCC can be configured as serial (UART) or Ethernet (MII) for debug and control. Alternatively, the remaining UCC of the MPC8360E could be used to support an Ethernet connection to a low cost digital signal processor (DSP) such as the family of DSPs based on the StarCore technology supporting voice ports, which can be for plain old telephone system (POTS) telephones or for IP-based telephones using a combination of premium voice algorithms such as G729a/b, G723 ...
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... MPC8360E Features • High-performance, low power, and cost-effective communications processor • The MPC8360E QUICC Engine offers a future-proof solution for next generation designs by supporting programmable protocol termination, network interface termination, and interworking features to meet evolving protocol standards • Single platform architecture supports the convergence of IP packet networks and ATM networks, including interworking between these networks • ...
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... The QUICC Engine has the following features: • Two 32-bit RISC controllers for flexible support of the communications peripherals • Serial DMA channel for receive and transmit on all serial channels MPC8360E PowerQUICC II Freescale Semiconductor 2 C and SPI interfaces. ™ ...
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... The UCCs are similar to the PowerQUICC II peripherals: SCC (BISYNC, UART, and HDLC bus), and FCC (fast Ethernet, HDLC, transparent, and ATM). In addition, 2×124 UTOPIA PHYs are supported in ATM mode. The QUICC Engine presents enhanced flexibility by allowing the user to configure the UCCs to support a Layer-2 Ethernet switch. MPC8360E PowerQUICC II 8 ™ Pro Processor Product Brief, Rev. 0 Preliminary— ...
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... Random number generator (RNG) • Four crypto-channels, each supporting multi-command descriptor chains 3.4 Dual DDR Memory Controllers The MPC8360E DDR memory controllers include the following features: • Programmable timing supporting DDR-1 SDRAM • Configurable as two 32-bit buses or one 64-bit bus • ...
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... FIFOs are supported for both the transmitter and the receiver. The MPC8360E local bus controller (LBC) port allows connections with a wide variety of external memories, DSPs, and ASICs. Three separate state machines share the same external pins and can be programmed separately to access different types of devices ...
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... Figure 5. Software Protocol Support for the QUICC Engine 5 Document Revision History Table 1 provides a revision history for this product brief. Rev. No. 0 Initial release. MPC8360E PowerQUICC II Freescale Semiconductor shows the wealth of communication protocols supported by the QUICC Customer Application RIP ARP OSPF QUICC Engine PROTOCOL DRIVER API ...
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... Denver, Colorado 80217 (800) 441-2447 303-675-2140 Fax: 303-675-2150 LDCForFreescaleSemiconductor @hibbertgroup.com Document Number: MPC8360EPB Rev. 0 04/2005 Preliminary—Subject to Change Without Notice Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document ...