MPC8360E-RDK Freescale Semiconductor, MPC8360E-RDK Datasheet
MPC8360E-RDK
Specifications of MPC8360E-RDK
Related parts for MPC8360E-RDK
MPC8360E-RDK Summary of contents
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... MPC8360E PowerQUICC II Pro Integrated Communications Processor Family Reference Manual, Rev locate any updates for this document, refer to the MPC8360E product summary page on our website listed on the back cover of this document or contact your Freescale sales office. © 2011 Freescale Semiconductor, Inc. All rights reserved. ...
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... Overview This section describes a high-level overview including features and general operation of the MPC8360E/58E PowerQUICC II Pro processor. A major component of this device is the e300 core, which includes 32 Kbytes of instruction and data cache and is fully compatible with the Power Architecture™ 603e instruction set. The new QUICC Engine module provides termination, interworking, and switching between a wide range of protocols including ATM, Ethernet, HDLC, and POS. The QUICC Engine module’ ...
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... Major features of the MPC8360E/58E are as follows: • e300 PowerPC processor core (enhanced version of the MPC603e core) — Operates 667 MHz (for the MPC8360E) and 400 MHz (for the MPC8358E) — High-performance, superscalar processor core — Floating-point, integer, load/store, system register, and branch processing units — ...
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... Overview — QUICC Engine module peripheral request interface (for SEC, PCI, IEEE Std. 1588™) — Eight universal communication controllers (UCCs) on the MPC8360E and six UCCs on the MPC8358E supporting the following protocols and interfaces (not all of them simultaneously): – IEEE 1588 protocol supported – ...
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... MultiPHY — Two serial peripheral interfaces (SPI); SPI2 is dedicated to Ethernet PHY management — Eight TDM interfaces on the MPC8360E and four TDM interfaces on the MPC8358E with 1-bit mode for E3/T3 rates in clear channel — Sixteen independent baud rate generators and 30 input clock pins for supplying clocks to UCC and MCC serial channels (MCC is only available on the MPC8360E) — ...
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... MPC8358E — Programmable timing supporting both DDR1 and DDR2 SDRAM — On the MPC8360E, the DDR buses can be configured as two 32-bit buses or one 64-bit bus; on the MPC8358E, the DDR bus can be configured as a 32- or 64-bit bus — 32- or 64-bit data interface 333 MHz (for the MPC8360E) and 266 MHz (for the MPC8358E) data rate — ...
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... Four groups of interrupts with programmable priority — External and internal interrupts directed to communication processor — Redirects interrupts to external INTA pin when in core disable mode — Unique vector number for each interrupt source MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor Overview 7 ...
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... Electrical Characteristics This section provides the AC and DC electrical specifications and thermal characteristics for the MPC8360E/58E. The device is currently targeted to these specifications. Some of these specifications are independent of the I/O cell, but are included for a more complete reference. These are not purely I/O buffer design specifications ...
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... IN REF the PCI interface may overshoot/undershoot according to the PCI Electrical Specification for 3.3-V operation shown in Figure 4. MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor Table 1. Absolute Maximum Ratings Symbol DDR ...
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... negative direction. 2. The operating conditions for junction temperature, T 0° °C. Refer to Errata General9 in Chip Errata for the MPC8360E, Rev MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev DDR DDR2 2 C, SPI, must track each other and must vary in the same direction—either in the positive the 600/333/400 MHz and 500/333/500 MHz on rev ...
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... PCI interface of the device for the 3.3-V signals, respectively. Overvoltage Waveform Undervoltage Waveform Figure 4. Maximum AC Waveforms on PCI interface for 3.3-V Signaling MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor + 5% DD GND Not to Exceed 10 interface refers to the clock period associated with the bus clock interface ...
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... In the case where the core voltage is applied first, the core voltage supply must rise to 90% of its nominal value before the I/O supplies reach 0.7 V, see MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev Table 3. Output Drive Capability Output Impedance (Ω ...
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... I/O voltage supplies ( another. 2.2.2 Power-Down Sequencing The MPC8360E/58E does not require the core supply voltage and I/O supply voltages to be powered down in any particular order. 3 Power Characteristics The estimated typical power dissipation values are shown in Table 4. MPC8360E TBGA Core Power Dissipation ...
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... Typical power is based on a voltage of V application. 3. Thermal solutions will likely need to design to a value higher than typical power on the end application, T power. 4. Maximum power is based on a voltage of V MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev QUICC Engine Frequency (MHz) 500 ...
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... Clock Input Timing This section provides the clock input DC and AC electrical characteristics for the MPC8360E/58E. The rise/fall time on QUICC Engine block input pins should not exceed 5 ns. This should be enforced especially on clock signals. Rise time refers to signal transitions from 10 from 90 MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2 ...
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... This represents the total input jitter—short term and long term—and is guaranteed by design. 5. The CLKIN/PCI_CLK driver’s closed loop jitter bandwidth should be <500 kHz at –20 dB. The bandwidth must be set low to allow cascade-connected PLL-based devices to track CLKIN drivers with the specified jitter. MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev Condition Symbol — ...
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... Table 10. RESET Pins DC Electrical Characteristics Characteristic Input high voltage Input low voltage Input current Output high voltage Output low voltage MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor = 2.5 ± 0.125 mV/ 3.3 V ± 165 mV DD Symbol Min t — ...
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... CLKIN only valid when the device is in PCI host mode. See the CLKIN MPC8360E PowerQUICC II Pro Integrated Communications Processor Family Reference Manual for more details. 3. POR config signals consists of CFG_RESET_SOURCE[0:2] and CFG_CLKIN_DIV. MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev Symbol Condition ...
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... RMII GMII/RGMII/TBI/RTBI SPI (master/slave) UCC through TDM MCC UTOPIA L2 POS-PHY L2 HDLC bus HDLC/transparent MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor Table 12. PLL and DLL Lock Times Min — 7680 Section 22, “Clocking,” NOTE Interface Operating ...
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... Output high current (V = 1.420 V) OUT Output low current (V = 0.280 V) OUT MV input leakage current REF MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev Interface Operating Max Interface Bit Frequency (MHz) Rate (Mbps) 3.68 (max internal ref clock) 2 (max) 48 (ref clock) ...
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... It is the supply to which far end signal termination is made and is expected equal This rail should track variations in the DC level of MV REF 4. Output leakage is measured with all outputs disabled MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor Symbol Min I — ...
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... Parameter AC input low voltage AC input high voltage Note: 1. Maximum possible skew between a data strobe (MDQS[n]) and any corresponding bit of data (MDQ[8n + {0...7 ≤ n ≤ ECC (MECC[{0...7 8). MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev (typ Symbol C IO ...
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... Table 21. DDR and DDR2 SDRAM Output AC Timing Specifications for Source At recommended operating conditions with GV 8 Parameter MCK[n] cycle time, (MCK[n]/MCK[n] crossing) Skew between any MCK to ADDR/CMD MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor of (1.8 or 2.5 V) ± 5%. DD Symbol Min ...
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... MCS(n) output hold with respect to MCK MCK to MDQS MDQ/MECC/MDM output setup with respect to MDQS MDQ/MECC/MDM output hold with respect to MDQS MDQS preamble start MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev Synchronous Mode (continued 2.5 V) ± 5%. DD ...
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... CLK_CNTL register. The timing parameters listed in the table assume that these two parameters have been set to the same adjustment value. See the MPC8360E PowerQUICC II Pro Integrated Communications Processor Family Reference Manual for a description and understanding of the timing modifications enabled by use of these bits ...
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... AC test load for the DDR bus. Output Table 22. DDR and DDR2 SDRAM Measurement Conditions Symbol OUT Notes: 1. Data input threshold measurement point. 2. Data output measurement point. MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev MCK[n] MCK[n] t MCK t AOSKEW(max) CMD t AOSKEW(min) CMD AOSKEW = 50 Ω ...
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... High-level output voltage 100 μA Low-level output voltage Input current (0 V ≤V ≤ Note: 1. Note that the symbol this case, represents the OV IN MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor t MCK DDKHAS DDKHCS DDKHAX DDKHCX NOOP DDKHMP ...
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... V. The RGMII and RTBI interfaces follow the Reduced Gigabit Media-Independent Interface (RGMII) Specification Version 1.3. The RMII interface follows the RMII Consortium RMII Specification Version 1.2. MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev Table 24. DUART AC Timing Specifications Parameter Section 8.3, “ ...
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... Parameter/Condition GTX_CLK clock period GTX_CLK duty cycle GTX_CLK to GMII data TXD[7:0], TX_ER, TX_EN delay GTX_CLK clock rise time, (20% to 80%) MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor UCC Ethernet Controller: Three-Speed Ethernet, MII Management Conditions — ...
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... At recommended operating conditions with LV Parameter/Condition RX_CLK clock period RX_CLK duty cycle RXD[7:0], RX_DV, RX_ER setup time to RX_CLK RXD[7:0], RX_DV, RX_ER hold time to RX_CLK RX_CLK clock rise time, (20% to 80%) MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev /OV of 3.3 V ± 10 ...
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... TX_CLK clock period 10 Mbps TX_CLK clock period 100 Mbps TX_CLK duty cycle TX_CLK to MII data TXD[3:0], TX_ER, TX_EN delay MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor UCC Ethernet Controller: Three-Speed Ethernet, MII Management /OV of 3.3 V ± 10%. ...
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... RX_CLK clock period 10 Mbps RX_CLK clock period 100 Mbps RX_CLK duty cycle RXD[3:0], RX_DV, RX_ER setup time to RX_CLK RXD[3:0], RX_DV, RX_ER hold time to RX_CLK RX_CLK clock rise time, (20% to 80%) MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev /OV of 3.3 V ± 10 ...
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... Figure 13 provides the AC test load. Output Figure 14 shows the MII receive AC timing diagram. RX_CLK RXD[3:0] RX_DV RX_ER MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor UCC Ethernet Controller: Three-Speed Ethernet, MII Management /OV of 3.3 V ± 10 Symbol t ...
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... For example, the subscript of t convention is used with the appropriate letter: R (rise (fall). Figure 15 shows the RMII transmit AC timing diagram. REF_CLK TXD[1:0] TX_EN Figure 15. RMII Transmit AC Timing Diagram MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev /OV of 3.3 V ± 10 Symbol t ...
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... Figure 16 provides the AC test load. Output Figure 17 shows the RMII receive AC timing diagram. REF_CLK RXD[1:0] CRS_DV RX_ER MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor UCC Ethernet Controller: Three-Speed Ethernet, MII Management /OV of 3.3 V ± 10 Symbol t ...
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... This symbol is used to represent the external GTX_CLK125 and does not follow the original symbol naming convention rev. 2.0 silicon, due to errata, t TTKHDX MPC8360E, Rev Figure 18 shows the TBI transmit AC timing diagram. GTX_CLK TXD[7:0] TX_EN TX_ER MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev /OV of 3.3 V ± 10 Symbol t TTX ...
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... RCG are measured from riding edge of PMA_RX_CLK0. Figure 19 shows the TBI receive AC timing diagram. PMA_RX_CLK1 RCG[9:0] PMA_RX_CLK0 MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor UCC Ethernet Controller: Three-Speed Ethernet, MII Management /OV of 3.3 V ± 10%. DD ...
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... UCC2 option 2. In rev. 2.1 silicon, due to errata, t and –0.9 for UCC2 option 2, and t SKRGTKHDV Refer to Errata QE_ENET10 in Chip Errata for the MPC8360E, Rev UCC1 does meet t silicon. MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 ...
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... Table 36. MII Management DC Electrical Characteristics When Powered at 3.3 V Parameter Supply voltage (3.3 V) Output high voltage Output low voltage Input high voltage MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor UCC Ethernet Controller: Three-Speed Ethernet, MII Management t RGTH t ...
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... MHz; for a csb_clk of 375 MHz, the maximum frequency is 11.7 MHz and the minimum frequency is 1.7 MHz). 3. This parameter is dependent on the ce_clk speed (that is, for a ce_clk of 200 MHz, the delay and for a ce_clk of 300 MHz, the delay is 63 ns). MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev Symbol Conditions V — ...
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... These are asynchronous signals. 3. Inputs need to be stable at least one TMR clock. 9 Local Bus This section describes the DC and AC electrical specifications for the local bus interface of the MPC8360E/58E. MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor t MDC t t ...
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... Local bus clock to data valid for LAD/LDP Local bus clock to address valid for LAD Output hold from local bus clock (except LAD/LDP and LALE) Output hold from local bus clock for LAD/LDP MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev Symbol Min ...
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... LALE output fall to LAD output transition (LATCH hold time) LALE output fall to LAD output transition (LATCH hold time) LALE output fall to LAD output transition (LATCH hold time) Local bus clock to output valid MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor Symbol t ...
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... DLL bypass mode is not recommended for use at frequencies above 66 MHz. Figure 22 provides the AC test load for the local bus. Output MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev Symbol t LBKHOZ (first two letters of functional block)(signal)(state)(reference)(state) for outputs ...
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... Input Signal: LGTA Output Signals: LSDA10/LSDWE/LSDRAS/ LSDCAS/LSDDQM[0:3] LA[27:31]/LBCTL/LBCKE/LOE/ Output Signals: LAD[0:31]/LDP[0:3] LALE Figure 24. Local Bus Signals, Nonspecial Signals Only (DLL Bypass Mode) MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor t LBIVKH t t LBKHOX LBKHOV t LBKHOZ ...
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... UPM Mode Input Signal: LUPWAIT Input Signals: LAD[0:31]/LDP[0:3] (DLL Bypass Mode) UPM Mode Output Signals: LCS[0:3]/LBS[0:3]/LGPL[0:5] Figure 26. Local Bus Signals, GPCM/UPM Signals for LCRR[CLKDIV (DLL Bypass Mode) MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev LBKHOZ1 t LBKHOV1 t LBIVKH2 ...
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... LUPWAIT Input Signals: LAD[0:31]/LDP[0:3] (DLL Bypass Mode) UPM Mode Output Signals: LCS[0:3]/LBS[0:3]/LGPL[0:5] Figure 27. Local Bus Signals, GPCM/UPM Signals for LCRR[CLKDIV (DLL Bypass Mode) MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor t LBKHOZ t LBKHOV t ...
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... DC electrical characteristics for the IEEE 1149.1 (JTAG) interface of the device. Table 42. JTAG interface DC Electrical Characteristics Characteristic Output high voltage Output low voltage Output low voltage Input high voltage Input low voltage Input current MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev LBKHOZ1 t LBKHOV1 t LBIVKH2 t ...
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... TRST is an asynchronous level sensitive signal. The setup time is for test purposes only. 4. Non-JTAG signal input timing with respect Non-JTAG signal output timing with respect Guaranteed by design and characterization. MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor Table 2). ...
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... TRST Figure 32 provides the boundary-scan timing diagram. JTAG External Clock Boundary Data Inputs t JTKLDX Boundary Data Outputs Boundary Output Data Valid Data Outputs MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev Ω JTKHKL t JTG VM = Midpoint Voltage (OV DD /2) VM ...
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... JTAG External Clock TDI, TMS t JTKLOX TDO TDO Output Data Valid Figure 33. Test Access Port Timing Diagram MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor JTIVKH Input Data Valid t JTKLOV ...
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... Notes: 1. Output voltage (open drain or open collector) condition = 3 mA sink current capacitance of one bus line in pF Refer to the MPC8360E Integrated Communications Processor Family Reference Manual for information on the digital filter used. 4. I/O pins will obstruct the SDA and SCL lines 11.2 ...
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... AC test load for the I Output Figure 35 shows the AC timing diagram for the I SDA t I2CF t I2CL SCL t I2SXKL S MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor Electrical Specifications (continued) Table 44). Symbol t I2DXKL CBUS compatible masters bus devices ...
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... For example, t symbolizes PCI timing (PC) with respect to the time hard reset PCRHFV maximum is 6.6 ns. Refer to Errata PCI21 in Chip Errata for the MPC8360E, Rev minimum is 1 ns. Refer to Errata PCI17 in Chip Errata for the MPC8360E, Rev Min Max 0.5 × ...
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... PCIVKH t PCIXKH (first two letters of functional block)(signal)(state)(reference)(state) for outputs. For example, t symbolizes PCI timing (PC) with respect to the time hard reset PCRHFV minimum is 1 ns. Refer to Errata PCI17 in Chip Errata for the MPC8360E, Rev Ω Ω Figure 36. PCI AC Test Load ...
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... Output Delay High-Impedance Output Figure 38. PCI Output AC Timing Measurement Condition 13 Timers This section describes the DC and AC electrical specifications for the timers of the MPC8360E/58E. 13.1 Timers DC Electrical Characteristics Table 49 provides the DC electrical characteristics for the device timer pins, including TIN, TOUT, TGATE, and RTC_CLK. ...
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... Figure 39 provides the AC test load for the timers. Output 14 GPIO This section describes the DC and AC electrical specifications for the GPIO of the MPC8360E/58E. 14.1 GPIO DC Electrical Characteristics Table 51 provides the DC electrical characteristics for the device GPIO. Table 51. GPIO DC Electrical Characteristics Characteristic Output high voltage ...
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... IPIC inputs and outputs are asynchronous to any visible clock. IPIC outputs should be synchronized before use by any external synchronous logic. IPIC inputs are required to be valid for at least t in edge triggered mode. 16 SPI This section describes the DC and AC electrical specifications for the SPI of the MPC8360E/58E. MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev Ω ...
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... Figure 41 provides the AC test load for the SPI. Output MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor Table 55. SPI DC Electrical Characteristics Symbol Condition – ...
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... Table 57 provides the DC electrical characteristics for the device TDM/SI. Table 57. TDM/SI DC Electrical Characteristics Characteristic Output high voltage Output low voltage Input high voltage MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev Table 56. Note that although the specifications t NEIXKH t ...
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... AC test load for the TDM/SI. Output Figure 45 represents the AC timing from reference the rising edge of the clock, these AC timing diagrams also apply when the falling edge is the active edge. MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor Symbol Condition V — ...
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... UTOPIA input and output AC timing specifications. Table 60. UTOPIA AC Timing Specifications Characteristic UTOPIA outputs—Internal clock delay UTOPIA outputs—External clock delay UTOPIA outputs—Internal clock high impedance UTOPIA outputs—External clock high impedance MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev SEIXKH t SEKHOV t ...
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... Figure 47 shows the UTOPIA timing with external clock. UtopiaCLK (Input) t UEIVKH Input Signals: UTOPIA Output Signals: UTOPIA Figure 47. UTOPIA AC Timing (External Clock) Diagram MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor 2 Symbol t UIIVKH t UEIVKH t UIIXKH t ...
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... UART protocols. Table 61. HDLC, BISYNC, Transparent, and Synchronous UART DC Electrical Characteristics Characteristic Output high voltage Output low voltage Input high voltage Input low voltage Input current MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev UIIXKH t UIIVKH t UIKHOV ...
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... The symbols used for timing specifications follow the pattern of t inputs and t (first two letters of functional block)(reference)(state)(signal)(state) internal timing (HI) for the time t serial MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor HDLC, BISYNC, Transparent, and Synchronous UART Symbol t ...
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... Serial CLK (Output) Input Signals: (See Note) Output Signals: (See Note) Note: The clock edge is selectable. Figure 51. AC Timing (Internal Clock) Diagram MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev Ω Figure 49. AC Test Load Table 62 ...
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... USB receive signals skew (RS) among RXP, RXN, and RXD (PND). Also, t transmit signals skew (TS) between TXP and TXN (PN). 2.Skew measurements are done at OV Figure 52 provide the AC test load for the USB. Output MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor Table 64. USB DC Electrical Characteristics Symbol V V ...
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... Package outline Interconnects Pitch Module height (typical) Solder Balls Ball diameter (typical) MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev Section 21.1, “Package Parameters for the TBGA Package,” for information on the package. 37.5 mm × 37.5 mm 740 1. ...
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... Mechanical Dimensions of the TBGA Package Figure 53 depicts the mechanical dimensions and bottom surface nomenclature of the device, 740-TBGA package. Figure 53. Mechanical Dimensions and Bottom Surface Nomenclature of the TBGA Package MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor Package and Pin Listings 69 ...
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... MEMC1_MODT[2:3]/ MEMC2_MODT[0:1] MEMC1_MWE MEMC1_MRAS MEMC1_MCAS MEMC1_MCS[0:1] MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev Table 66. MPC8360E TBGA Pinout Listing Package Pin Number AJ34, AK33, AL33, AL35, AJ33, AK34, AK32, AM36, AN37, AN35, AR34, AT34, AP37, AP36, AR36, AT35, AP34, AR32, AP32, AM31, AN33, ...
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... PCI_AD[31:30]/CE_PG[31:30] PCI_AD[29:25]/CE_PG[29:25] PCI_AD[24]/CE_PG[24] PCI_AD[23:0]/CE_PG[23:0] PCI_C/BE[3:0]/CE_PF[10:7] PCI_PAR/CE_PF[11] PCI_FRAME/CE_PF[12] PCI_TRDY/CE_PF[13] MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor Package Pin Number AU8, AU7 AL32, AU33 AK37, AT37 AN1, AR2 AN25, AK1 AL37, AT36 ...
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... LDP[3]/LCS[7] LA[27:31] LCS[0:5] LWE[0:3]/LSDDQM[0:3]/LBS[0:3] LBCTL LALE LGPL0/LSDA10/cfg_reset_source0 LGPL1/LSDWE/cfg_reset_source1 LGPL2/LSDRAS/LOE LGPL3/LSDCAS/cfg_reset_source2 LGPL4/LGTA/LUPWAIT/LPBSE LGPL5/cfg_clkin_div LCKE MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev Package Pin Number C28 B28 E26 F22 B29 A29 F19 A21 C21 E20 B20 ...
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... M2SRCID[3]/LSRCID[3] IIC1_SDA IIC1_SCL IIC2_SDA IIC2_SCL CE_PA[0] CE_PA[1:2] CE_PA[3:7] CE_PA[8] CE_PA[9:12] CE_PA[13:14] CE_PA[15] MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor Package Pin Number J33 J34 G37 F34 G35 Programmable Interrupt Controller E34 C37 F35 F36 ...
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... PCI_CLK_OUT[0]/CE_PF[26] PCI_CLK_OUT[1:2]/CE_PF[27:28] CLKIN PCI_CLOCK/PCI_SYNC_IN PCI_SYNC_OUT/CE_PF[29] TCK TDI TDO TMS TRST MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev Package Pin Number AF4 B16, A16, E17, A17, B17 AF3 C18, D18, E18, A18 AF2, AE6 B19 AE5 ...
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... SRESET THERM0 THERM1 GND GV DD MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor Package Pin Number L35 AU34 PMC B36 System Control L37 L36 M33 Thermal Management AP19 AT31 Power and Ground Signals K35 K36 AM29 ...
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... DD MVREF1 MVREF2 SPARE1 SPARE3 SPARE4 SPARE5 MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev Package Pin Number D5, D6 C17, D16 B18, E21 C36, D29, D35, E16, F9, F12, F15, F17, F18, F20, F21, F23, F25, F26, F29, F31, F32, F33, G6, J6, ...
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... This pin must always be tied to GND. 8. This pin must always be left not connected. 9. Refers to MPC8360E PowerQUICC II Pro Integrated Communications Processor Family Reference Manual section on “RGMII Pins,” for information about the two UCC2 Ethernet interface options. 10 recommended that MDIC0 be tied to GND using an 18.2 Ω resistor and MDIC1 be tied to DDR power using an 18.2 Ω ...
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... PCI_SERR/CE_PF[18] PCI_PERR/CE_PF[19] PCI_REQ[0]/CE_PF[20] PCI_REQ[1]/CPCI_HS_ES/ CE_PF[21] PCI_REQ[2]/CE_PF[22] PCI_GNT[0]/CE_PF[23] PCI_GNT[1]/CPCI1_HS_LED/ CE_PF[24] MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev Package Pin Number AG33, AJ36, AT1, AK2 AT26 AT29 AT24 AU27, AT27, AU8, AU7 AL32, AU33 ...
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... LCLK[2]/LCS[7] LSYNC_OUT LSYNC_IN MCP_OUT IRQ0/MCP_IN IRQ[1]/M1SRCID[4]/M2SRCID[4]/ LSRCID[4] MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor Package Pin Number C20 D36 B37 Local Bus Controller Interface N32, N33, N35, N36, P37, P32, P34, R36, R35, ...
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... CE_PA[0] CE_PA[1:2] CE_PA[3:7] CE_PA[8] CE_PA[9:12] CE_PA[13:14] CE_PA[15] CE_PA[16] CE_PA[17:21] CE_PA[22] CE_PA[23:26] CE_PA[27:28] CE_PA[29] CE_PA[30] CE_PA[31] MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev Package Pin Number F36 H34 G33, G32 E35 H36 DUART E32 B34 C34 A35 Interface ...
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... TMS TRST TEST TEST_SEL QUIESCE MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor Package Pin Number AE2, AE1, AD5, AD3, AD2, AC6, AC5, AC4, AC2, AC1, AB5, AB4, AB3, AB1, AA6, AA4, AA2, Y6, Y4, Y3, Y2, Y1, W6, W5, W2, V5, V3, V2 ...
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... GND MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev Package Pin Number L37 L36 M33 Thermal Management AP19 AT31 Power and Ground Signals K35 K36 AM29 K37 A2, A8, A13, A19, A22, A25, A31, A33, A36, B7, B12, B24, B27, B30, C4, C6, C9, C15, C26, C32, ...
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... MVREF1 MVREF2 SPARE1 SPARE3 SPARE4 SPARE5 MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor Package Pin Number C17, D16 B18, E21 C36, D29, D35, E16, F9, F12, F15, F17, F18, F20, F21, F23, F25, F26, F29, F31, F32, F33, G6, J6, ...
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... This pin must always be tied to GND. 8. This pin must always be left not connected. 9. Refers to MPC8360E PowerQUICC II Pro Integrated Communications Processor Family Reference Manual section on “RGMII Pins,” for information about the two UCC2 Ethernet interface options. 10.This pin must always be tied recommended that MDIC0 be tied to GND using an 18.2 Ω ...
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... Figure 54 shows the internal distribution of clocks within the MPC8360E. MPC8360E ce_clk to QUICC Engine Block QUICC Engine PLL CFG_CLKIN_DIV CLKIN MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor e300 Core Core PLL csb_clk DDRC1 ddr1_clk DDRC2 Clock ...
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... PCI_SYNC_OUT and PCI_CLK_OUT. The CFG_CLKIN_DIV configuration input selects whether CLKIN or CLKIN/2 is driven out on the PCI_SYNC_OUT signal. The OCCR[PCIOENn] parameters enable the PCI_CLK_OUTn, respectively. MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev e300 Core Core PLL ...
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... Note that lb_clk is not the external local bus or DDRC2 frequency; lb_clk passes through the a LB clock divider to create the external local bus clock outputs (LSYNC_OUT and LCLK[0:2]). The LB clock divider ratio is controlled by LCRR[CLKDIV]. MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor 55, the primary clock input (frequency) is multiplied by the QUICC ...
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... The local bus frequency is 1/2, 1/4, or 1/8 of the lb_clk frequency (depending on LCRR[CLKDIV]) which is in turn 1× or 2× the csb_clk frequency (depending on RCWL[LBCM]). MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev Table 68 specifies which units have a configurable clock Table 68 ...
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... The RCWL[SVCOD] denotes the system PLL VCO internal frequency as shown in The VCO divider must be set properly so that the system VCO frequency is in the range of 600–1400 MHz. MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor Table 70. System PLL Multiplication Factors ...
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... Low 0000 High 0010 High 0011 High 0100 High 0101 MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev the LBCM, DDRCM, and SPMF parameters in the reset Table 72. CSB Frequency Options csb_clk : 16.67 2 Input Clock Ratio 2:1 3:1 4:1 ...
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... RCWL[COREPLL] selects the ratio between the internal coherent system bus clock (csb_clk) and the e300 core clock (core_clk). Table 73 in Table 73 should be considered reserved. RCWL[COREPLL] 0– MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor csb_clk : 2 Input Clock Ratio 6:1 7:1 8:1 9:1 10:1 11:1 12:1 13:1 14:1 15:1 16:1 shows the encodings for RCWL[COREPLL] ...
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... The QUICC Engine block PLL is controlled by the RCWL[CEPMF], RCWL[CEPDF], and RCWL[CEVCOD] parameters. block PLL. Table 74. QUICC Engine Block PLL Multiplication Factors RCWL[CEPMF] RCWL[CEPDF] 00000 00001 00010 00011 00100 MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev core_clk : csb_clk Ratio 2–5 6 0001 1 1.5:1 0010 ...
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... MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor QUICC Engine PLL Multiplication Factor = RCWL[CEPMF RCWL[CEPDF]) 0 × × × × × × ...
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... The QUICC Engine block VCO frequency is derived from the following equations: ce_clk = (primary clock input × CEPMF) ÷ CEPDF) QE VCO Frequency = ce_clk × VCO divider × CEPDF) MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev QUICC Engine PLL ...
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... MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor shows suggested PLL configurations for 33 and 66 MHz input clocks and for the appropriate operating frequencies for your Table 76. Suggested PLL Configurations Input CSB Freq ...
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... Select a suitable CSB and core clock rates from configuration bits. 3. Select a suitable QUICC Engine block clock rate from configuration bits. 4. Insert the chosen SPMF, COREPLL, CEPMF and CEPDF to the RCWL fields, respectively. MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev Input CSB Freq Core Freq ...
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... Junction-to-ambient (@1 m/s) on single-layer board (1s) Junction-to-ambient (@ 1 m/s) on four-layer board (2s2p) Junction-to-ambient (@ 2 m/s) on single-layer board (1s) Junction-to-ambient (@ 2 m/s) on four-layer board (2s2p) Junction-to-board thermal Junction-to-case thermal MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor Example 1. Sample Table Use Input Clock CSB Freq (MHz) ...
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... The thermal performance of any component is strongly dependent on the power dissipation of surrounding components. In addition, the ambient temperature varies widely within the application. For many natural convection and especially closed box applications, the board temperature at the perimeter MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev × I ...
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... When a heat sink is used, the thermal resistance is expressed as the sum of a junction to case thermal resistance and a case to ambient thermal resistance θ θ θ where junction-to-ambient thermal resistance (°C/W) θ JA MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor ) D ) can be used to determine the junction temperature with Thermal 99 ...
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... Simplified thermal models of the packages can be assembled using the junction-to-case and junction-to-board thermal resistances listed in the thermal resistance table. More detailed thermal models can be made available on request. MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 100 . For instance, the user can change the size of the heat θ ...
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... Dow-Corning Corporation Dow-Corning Electronic Materials 2200 W. Salzburg Rd. Midland, MI 48686-0997 Internet: www.dowcorning.com Shin-Etsu MicroSi, Inc. 10028 S. 51st St. Phoenix, AZ 85044 Internet: www.microsi.com MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor 603-224-9988 408-749-7601 818-842-7277 408-436-8770 800-522-6752 603-635-5102 781-935-4850 800-248-2481 ...
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... D 24 System Design Information This section provides electrical and thermal design recommendations for successful application of the MPC8360E/58E. Additional information can be found in MPC8360E/MPC8358E PowerQUICC Design Checklist (AN3097). MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 102 800-347-4572 ) D Freescale Semiconductor ...
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... Therefore recommended that the system designer place at least one decoupling capacitor at each V decoupling capacitors should receive their power from separate V MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor 1) generates the platform clock from the externally supplied CLKIN Section 22.1, “ ...
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... When data is held high, SW1 is closed (SW2 is open) and R OV /2. R then becomes the resistance of the pull-up devices other in value. Then MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 104 , and LV planes, to enable quick recharging of the smaller chip ...
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... HRESET is asserted, is latched when HRESET deasserts, at which time the input receiver is disabled and the I/O circuit takes on its normal function. Careful board layout with stubless connections to these MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor ...
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... Processor core frequencies supported by parts addressed by this specification only. Not all parts described in this specification support all core frequencies. Additionally, parts addressed by part number specifications may support other maximum core frequencies. MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 106 Table 80. Part Numbering Nomenclature ...
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... CLKIN/2 is driven out on the PCI_CLK_OUTn signals.” • In Section 22.1, “System PLL • In Table 80, added extended temperature characteristics. 2 12/2007 Initial release. MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor Table 81. SVR Settings SVR Package (Rev. 2.0) TBGA 0x8048_0020 ...
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... Literature Distribution Center 1-800 441-2447 or +1-303-675-2140 Fax: +1-303-675-2150 LDCForFreescaleSemiconductor @hibbertgroup.com Document Number: MPC8360EEC Rev. 4 01/2011 Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document ...