74LVX273M Fairchild Semiconductor, 74LVX273M Datasheet

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74LVX273M

Manufacturer Part Number
74LVX273M
Description
IC FLIP FLOP OCTAL D-TYPE 20SOIC
Manufacturer
Fairchild Semiconductor
Series
74LVXr
Type
D-Type Busr
Datasheet

Specifications of 74LVX273M

Function
Master Reset
Output Type
Non-Inverted
Number Of Elements
1
Number Of Bits Per Element
8
Frequency - Clock
150MHz
Delay Time - Propagation
7.1ns
Trigger Type
Positive Edge
Current - Output High, Low
4mA, 4mA
Voltage - Supply
2 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
20-SOIC (7.5mm Width)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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© 2005 Fairchild Semiconductor Corporation
74LVX273M
74LVX273SJ
74LVX273MTC
74LVX273
Low Voltage Octal D-Type Flip-Flop
General Description
The LVX273 has eight edge-triggered D-type flip-flops with
individual D inputs and Q outputs. The common buffered
Clock (CP) and Master Reset (MR) input load and reset
(clear) all flip-flops simultaneously.
The register is fully edge-triggered. The state of each D
input, one setup time before the LOW-to-HIGH clock transi-
tion, is transferred to the corresponding flip-flop’s Q output.
All outputs will be forced LOW independently of Clock or
Data inputs by a LOW voltage level on the MR input. The
device is useful for applications where the true output only
is required and the Clock and Master Reset are common to
all storage elements. The inputs tolerate up to 7V allowing
interface of 5V systems to 3V systems.
Ordering Code:
Devices also available in Tape and Reel. Specify by appending letter suffix “X” to the ordering code.
Pb-Free package per JEDEC J-STD-020B.
Logic Symbols
Pin Descriptions
Order Number
D
MR
CP
Q
0
0
–D
–Q
Pin Names
7
7
Package Number
Data Inputs
Master Reset
Clock Pulse Input
Data Outputs
MTC20
IEEE/IEC
M20B
M20D
Description
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
DS011614
Features
Connection Diagram
Truth Table
H
L
Reset (Clear)
Load '1'
Load '0'
Operating Mode
Input voltage translation from 5V to 3V
Ideal for low power/low noise 3.3V applications
Guaranteed simultaneous switching noise level and
dynamic threshold performance
LOW Voltage Level
HIGH Voltage Level
Package Description
MR
H
H
L

X
LOW-to-HIGH Transition
June 1993
Revised April 2005
Immaterial
Inputs
CP


X
www.fairchildsemi.com
D
X
H
L
n
Outputs
Q
H
L
L
n

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74LVX273M Summary of contents

Page 1

... Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide 74LVX273SJ M20D Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74LVX273MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Devices also available in Tape and Reel. Specify by appending letter suffix “X” to the ordering code. ...

Page 2

Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. www.fairchildsemi.com 2 ...

Page 3

Absolute Maximum Ratings Supply Voltage ( Input Diode Current ( 0. Input Voltage ( Output Diode Current ( 0. 0.5V ...

Page 4

AC Electrical Characteristics V CC Symbol Parameter (V) t Propagation 2.7 PLH t Delay Time PHL 3 Propagation Delay 2.7 PHL 3.3 t Setup Time 2 ...

Page 5

Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Package Number M20B 5 www.fairchildsemi.com ...

Page 6

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide www.fairchildsemi.com Package Number M20D 6 ...

Page 7

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves ...

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