E28F002-BCT-80 Intersil, E28F002-BCT-80 Datasheet
E28F002-BCT-80
Related parts for E28F002-BCT-80
E28F002-BCT-80 Summary of contents
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VOLT BOOT BLOCK FLASH MEMORY n High Performance Read 80/120 ns Max. Access Time 40 ns Max. Output Enable Time n Low Power Consumption 20 mA Typical Read Current n x8-Only Input/Output Architecture Space-Constrained 8-bit Applications n Optimized Array ...
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Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of Sale ...
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INTRODUCTION............................................. 5 1.1 Designing for Density Upgradeability ........... 5 1.2 Main Features.............................................. 5 1.3 Applications ................................................. 6 1.4 Pinouts ........................................................ 7 1.5 Pin Descriptions......................................... 10 2.0 PRODUCT DESCRIPTION ........................... 11 2.1 Memory Organization ................................ 12 2.1.1 Blocking .............................................. 12 ...
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REVISION HISTORY Date of Version Revision 04/01/96 -001 Original version 09/01/96 -002 Pin 2 of 44-Lead PSOP changed from Alternate program command (10H) removed WSM transition table added 10/01/96 -003 40-Lead PDIP package added Erase Suspend/Resume ...
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INTRODUCTION This datasheet comprises the specifications for the 28F002BC 2-Mbit flash memory. Section 1.0 provides an overview of the 2-Mbit flash memory, including applications, pinouts, and descriptions. Section 2.0 describes the memory organization in detail. Section 3.0 defines a ...
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Host Bus Main Memory Pentium® 82430FX Processor PCIset 100/90 MHz (82437FX) Cache Figure 1. 28F002BC-T Interface to a Pentium® Microprocessor System The Status Register (SR) indicates the status of the internal Write State Machine (WSM), which reports critical information ...
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... WP# input, is also shown in the same diagram. The 40-lead TSOP package (shown in Figure 2) offers the smallest form factor possible. The low- cost 40-lead PDIP package diagram is shown in Figure E28F002BC 32 Boot Block 31 40-Lead TSOP TOP VIEW ...
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CE# 4 GND 5 OE ...
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WP ...
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Pin Descriptions Table 1. 28F002BC Pin Descriptions Symbol Type ADDRESS INPUTS for memory addresses. Addresses are internally latched A , INPUT –1 during a write cycle – TSOP and PDIP packages. A INPUT ADDRESS ...
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PRODUCT DESCRIPTION Output Buffer Power Reduction Control Input Buffer Y-Decoder Address X-Decoder Latch Address Counter Figure 5. 28F002BC Internal Block Diagram PRELIMINARY DQ - Input Buffer Identifier Register Status Command Register User Interface ...
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Memory Organization 2.1.1 BLOCKING The 28F002BC features an asymmetrically-blocked architecture that provides system integration. Each block can be erased up to 100,000 times. The block sizes have been chosen to optimize their functionality for applications of nonvolatile storage. ...
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CUI. The purpose of the Write State Machine (WSM automate the write and erasure of the device completely. The WSM will begin operation upon receipt of a signal from the ...
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... Reading location 00001H outputs the device ID, 7CH. The 28F002BC device ID of 7CH is identical to the E28F002BX (40-lead TSOP). It differs from the PA28F200BX (44-lead PSOP), which has a device ID of 2274H. Designers using the PA28F200BX in the x8 mode who wish to migrate to the ...
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Table 4. Command Bus Definitions Command Notes Read Array Intelligent Identifier 1,2 Read Status Register Clear Status Register Program Setup Block Erase/Confirm Erase Suspend/Resume ADDRESS BA = Block Address SRD = Status Register Data IA = Identifier Address IID = ...
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Read Status Register (70H) This is one of three commands that is executable while the WSM is operating. After this command is written, a read of the device will output the contents of the status register, regardless of the ...
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Erase Resume (D0H) This command will cause the CUI to clear the Suspend state and clear the WSM status bit to a “0,” but only if an Erase Suspend command was previously issued. Erase Resume will not have any effect ...
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Table 5. Status Register Bit Definition WSMS ESS SR.7 = WRITE STATE MACHINE STATUS (WSMS Ready 0 = Busy SR.6 = ERASE-SUSPEND STATUS (ESS Erase Suspended 0 = Erase In Progress/Completed ...
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When the status register indicates that erasure is complete, the status bits, which indicate whether the erase operation was successful, should be checked. If the erase operation was unsuccessful, bit 5 of the status register will be set (within 1.5 ...
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Start Write 40H and Byte Address Write Data and Data Address Read Status Register No SR Yes Full Status Check if Desired Program Complete FULL STATUS CHECK PROCEDURE Read Status Register Data (See Above) 1 SR.3 ...
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Start Write 20H and Block Address Write D0H and Block Address Read Status Register Suspend Erase Loop 0 SR.7 = Suspend Erase Yes Full Status Check if Desired Program Complete FULL STATUS CHECK PROCEDURE Read Status Register Data (See Above) ...
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Start Write B0H Write 70H Read Status Register 0 SR SR.6 = Erase Resumed 1 Write FFH Read Array Data Done No Reading Yes Write D0H Write FFH Erase Resumed Read Array Data Figure 9. Erase ...
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Power Consumption 3.5.1 ACTIVE POWER With CE logic-low level and RP logic- high level, the device is placed in the active mode. The device I current is a maximum ...
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Power Supply Decoupling Flash memory’s power switching characteristics require careful device decoupling methods. System designers should consider three supply current issues: 1. Standby current levels (I ) CCS 2. Active current levels (I ) CCR 3. Transient peaks ...
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ELECTRICAL SPECIFICATIONS 4.1 Absolute Maximum Ratings* Operating Temperature During Read...............................0 °C to +70 °C During Write and Block Erase ....0 °C to +70 °C Temperature Bias................... –10 °C to +80 °C Storage Temperature ................. –65 °C to +125 °C ...
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DC Characteristics Symbol Parameter Notes I Input Load Current IL I Output Leakage Current Standby Current 1,3 CCS CC V Deep Power-Down I CC CCD Current V Read Current I 1,5 CC CCR I V ...
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DC Characteristics (Continued) Symbol Parameter Notes I RP# Boot Block Unlock 1,4 RP# Current A Intelligent Identifier I 1 Current A Intelligent Identifier Voltage V Input Low Voltage IL V Input High Voltage IH ...
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INPUT 0.8 0.45 NOTE: AC test inputs are driven for a logic “1” and V OH TTL and V (0 Output timing ends at V and V IL TTL IH ...
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AC Characteristics—Read-Only Operations Symbol Parameter t Read Cycle Time AVAV t Address to Output Delay AVQV t CE# to Output Delay ELQV t RP# to Output Delay PHQV t OE# to Output Delay GLQV t CE# to Output in ...
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Device and Address Selection V IH ADDRESSES (A) Address Stable CE# ( OE# ( WE# ( High Z DATA (D/ ...
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AC Characteristics—WE#-Controlled Write Operations Symbol Parameter t WE# Pulse Width High WHWL t Duration of Programming Operation WHQV1 t Duration of Erase Operation (Boot) WHQV2 t Duration of Erase Operation WHQV3 (Parameter) t Duration of Erase Operation (Main) WHQV4 ...
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ADDRESSES ( AVAV V IH CE# ( ELWL V IH OE# ( WE# ( High Z DATA (D/Q) D ...
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AC Characteristics—CE#-Controlled Write Operations Symbol Parameter t Write Cycle Time AVAV t RP# High Recovery to CE# Going PHEL Low t WE# Setup to CE# Going Low WLEL t Boot Block Lock Setup to CE# Going PHHEH High t ...
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ADDRESSES ( AVAV V IH CE# ( WLEL V IH OE# ( WE# ( High Z DATA (D/Q) D ...
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... PA = 44-Lead PSOP Product line designator ® for all Intel Flash products Device/Organization 00X= x8-only ( VALID COMBINATIONS: 40-Lead TSOP 40-Lead PDIP Commercial 2 M E28F002BC-T80 P28F002BC-T80 E28F002BC-T120 P28F002BC-T120 PRELIMINARY ± 10% ( ± ± 10 ± 10% ...
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ADDITIONAL INFORMATION Order Number 290580 3 Volt Advanced Boot Block Flash Memory; 28F004/400B3, 28F008/800B3, 28F016/160B3, 28F320B3 datasheet 292161 AP-608 Implementing a Plug and Play BIOS Using Intel’s Boot Block Flash Memory 292163 AP-610 Flash Memory In-System Code and ...
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WSM TRANSITION TABLE Write State Machine Current/Next States Current SR.7 Data Read Program State When Array Setup Read (FFH) (40H) Read Read Program Array “1” Array Array Setup Program Setup “1” Status * Program (Not “0” Status Comp.) Program Read ...