el5420t Intersil Corporation, el5420t Datasheet
el5420t
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el5420t Summary of contents
Page 1
... Other applications include battery power and portable devices, especially where low power consumption is important. The EL5420T is available TSSOP package SOIC package, and a space saving thermally enhanced 16 Ld QFN package. All feature a standard operational amplifier pin out. The devices operate over an ambient temperature range of -40° ...
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... Pinouts EL5420T (16 LD QFN) TOP VIEW VINA- 1 VINA+ 2 THERMAL PAD 3 VS+ VINB+ 4 THERMAL PAD CONNECTS TO VS- 2 EL5420T 12 VIND- 11 VIND+ 10 VS- 9 VINC+ EL5420T (14 LD TSSOP, SOIC) TOP VIEW VOUTA 1 14 VOUTD VINA VIND VINA VIND+ VS VS- VINB VINC+ ...
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... Supply Voltage Range Supply Current (Per Amplifier) S PSRR Power Supply Rejection Ratio DYNAMIC PERFORMANCE SR Slew Rate (Note 5) 3 EL5420T Thermal Information = +25°C) Thermal Resistance Junction-to-Ambient (Typical) - -0.5V +0. QFN (Note +0.5V)-(V - -0.5V SOIC (Note ...
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... Power Supply Rejection Ratio DYNAMIC PERFORMANCE SR Slew Rate (Note 5) t Settling to +0.1% (Note -3dB Bandwidth GBWP Gain-Bandwidth Product PM Phase Margin CS Channel Separation 4 EL5420T - = -5V 10kΩ +25°C, unless otherwise specified. (Continued CONDITIONS step, V OUTx R = 10kΩ 8pF ...
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... Settling time measured as the time from when the output level crosses the final value on rising/falling edge to when the output level settles within a ±0.1% error band. The range of the error band is determined by: Final Value(V)±[Full Scale(V)*0.1%] 5 EL5420T - = 0V 10kΩ +25° ...
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... INPUT OFFSET VOLTAGE DRIFT (|µV|/°C) FIGURE 3. INPUT OFFSET VOLTAGE DRIFT (QFN ± - TEMPERATURE (°C) FIGURE 5. INPUT BIAS CURRENT vs TEMPERATURE 6 EL5420T TYPICAL PRODUCTION DISTRIBUTION FIGURE 2. INPUT OFFSET VOLTAGE DRIFT (TSSOP, SOIC) TYPICAL PRODUCTION DISTRIBUTION -2 FIGURE 4. INPUT OFFSET VOLTAGE vs TEMPERATURE 4.95 4.93 4 ...
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... FIGURE 9. SLEW RATE vs TEMPERATURE 650 T = +25°C A 600 550 500 450 400 350 SUPPLY VOLTAGE (±V) FIGURE 11. SUPPLY CURRENT PER AMPLIFIER vs SUPPLY VOLTAGE 7 EL5420T (Continued) 140 120 100 -50 100 150 FIGURE 8. OPEN-LOOP GAIN vs TEMPERATURE 550 525 500 475 450 100 ...
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... 10kΩ 8pF 10k 100k FREQUENCY (Hz) FIGURE 17. MAXIMUM OUTPUT SWING vs FREQUENCY 8 EL5420T (Continued) 250 200 150 100 50 0 -50 10M 100M FIGURE 14. FREQUENCY RESPONSE FOR VARIOUS R 100pF 50pF 8pF 10M 100M FIGURE 16. CLOSED LOOP OUTPUT IMPEDANCE vs L ...
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... FREQUENCY (Hz) FIGURE 21. TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY 100 100 LOAD CAPACITANCE (pF) FIGURE 23. SMALL SIGNAL OVERSHOOT vs LOAD CAPACITANCE 9 EL5420T (Continued) 1M 10M FIGURE 20. INPUT VOLTAGE NOISE SPECTRAL DENSITY ± 10kΩ 1.4V IN RMS 10k 100k FIGURE 22 ...
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... VOUTB 8 7 VOUTC EL5420T (Continued ± +25° 10kΩ =8pF L 100mV STEP FIGURE 26. SMALL SIGNAL TRANSIENT RESPONSE EL5420T (14LD TSSOP/SOIC shown VOUTA VOUTD VINA- VIND VINA+ VIND+ 49 Vs+ Vs 4.7µF 0.1µF ...
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... VIND VOUTD 13, 16 pad Thermal Pad GND CIRCUIT 1 11 EL5420T FUNCTION Amplifier C Non-Inverting Input VS- Negative Power Supply Amplifier D Non-Inverting Input VIND- Amplifier D Inverting Input Amplifier D Output NC No Connect Functions as a heat sink. Connects to most negative potential, VS ...
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... This enables the amplifiers to offer maximum dynamic range at any supply voltage. Operating Voltage, Input and Output Capability The EL5420T can operate on a single supply or dual supply configuration. The EL5420T operating voltage ranges from a minimum of 4. maximum of 19V. This range allows for a standard 5V (or ± ...
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... EL5420T. A snubber is a shunt load consisting of a resistor in series with a capacitor. An optimized snubber can improve the phase margin and the stability of the EL5420T. The advantage of a snubber circuit is that it does not draw any DC load current or reduce the gain. Another method to reduce peaking is to add a series output resistor (typically between 1Ω ...
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... Power Supply Bypassing and Printed Circuit Board Layout The EL5420T can provide gain at high frequency, so good printed circuit board layout is necessary for optimum performance. Ground plane construction is highly recommended, trace lengths should be as short as possible and the power supply pins must be well bypassed to reduce any risk of oscillation ...
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... Plastic or metal protrusions of 0.006” maximum per side are not included. 2. Plastic interlead protrusions of 0.010” maximum per side are not included. 3. Dimensions “D” and “E1” are measured at Datum Plane “H”. 4. Dimensioning and tolerancing per ASME Y14.5M-1994 15 EL5420T D (N/2)+1 (N/2) H ...
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... BOTTOM VIEW 0. SEATING PLANE 0.08 C SEE DETAIL "X" N LEADS & EXPOSED PAD SIDE VIEW ( ( LEADS DETAIL X 16 EL5420T MDP0046 QFN (QUAD FLAT NO-LEAD) PACKAGE FAMILY (COMPLIANT TO JEDEC MO-220) B SYMBOL 0.075 PIN #1 I ...
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... However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 17 EL5420T MDP0044 A THIN SHRINK SMALL OUTLINE PACKAGE FAMILY SYMBOL PIN #1 I ...