EL5525 Intersil Corporation, EL5525 Datasheet
EL5525
Available stocks
Related parts for EL5525
EL5525 Summary of contents
Page 1
... The EL5525 has 18 outputs and comes in a 38-pin HTSSOP package specified for operation over the full -40°C to +85°C temperature range. Ordering Information PART TAPE & ...
Page 2
... Duty Cycle Duty Cycle for EXT_OSC Signal F_OSC Internal Refresh Oscillator Frequency INL Integral Nonlinearity Error DNL Differential Nonlinearity Error 2 EL5525 = 25°C) Ambient Operating Temperature . . . . . . . . . . . . . . . .-40°C to +85°C and +7(max) Maximum Die Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . 125°C S Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150° ...
Page 3
... OUTF 33 OUTE 34 OUTD 36 OUTC 37 OUTB 38 OUTA 3 EL5525 PIN TYPE Logic Input Chip select, low enables data input to logic Logic Input Serial data input Logic Input Serial data clock Logic Output Serial data output Input/Output Oscillator pin for synchronizing Power Positive supply voltage for analog circuits (4.5V - 16.5V) Power Positive power supply for digital circuites (3 ...
Page 4
... C =1nF L R =20Ω =180pF L M=400ns/DIV FIGURE 3. TRANSIENT LOAD REGULATION (SOURCING) SCLK SDA ENA OUTA M=200µs/DIV FIGURE 5. LARGE SIGNAL RESPONSE (RISING FROM 0V TO 8V) 4 EL5525 1.5 1 0.5 0 -0.5 -1 810 1010 5mA/DIV 5mA 0mA C =4.7nF L R =20Ω S 200mV/DIV FIGURE 4. TRANSIENT LOAD REGULATION (SINKING) ...
Page 5
... Each of the eight reference voltage outputs can be set with a 10-bit resolution. These outputs can be driven to within 50mV of the power rails of the EL5525. As all of the output buffers are identical also possible to use the EL5525 for applications other than LCDs where multiple voltage references are required that can be set to 10 bit accuracy ...
Page 6
... The output voltages from the EL5525 will be derived from the reference voltages present at the V pins. The impedance between those two pins is about 32kΩ. Care should be taken that the system design holds these two reference voltages within the limits of the power rails of the ≤ ...
Page 7
... In the worst-case scenario, this will be 860µs for EL5525, when the data has just missed the cycle at f_OSC = 21kHz. When a large change in output voltage is required, the change will occur in 2V steps, thus the requisite number of timing cycles will be added to the overall update time ...
Page 8
... Here, the OSC signal is synchronized to the load signal. The rising edge of the OSC signal is then delayed by some amount of time and gives enough time for charged to a new voltage before the switches are opened. 8 EL5525 CHANNEL TO CHANNEL REFRESH FIGURE 9. Ch1 --- Output1 Ch3 --- Output2 ...
Page 9
... Good printed circuit board layout is necessary for optimum performance. A low impedance and clean analog ground plane should be used for the EL5525. The traces from the two ground pins to the ground plane must be very short. The thermal pad of the EL5525 should be connected to the analog ground plane ...
Page 10
HTSSOP Package Outline Drawing - NOTE: The package drawing shown here may not be the latest version. To check the latest revision, please refer to the Intersil website at <http://www.intersil.com/design/packages/index.asp> ...
Page 11
... However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 11 EL5525 FN7393.1 August 1, 2005 ...