ISL22326 Intersil Corporation, ISL22326 Datasheet

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ISL22326

Manufacturer Part Number
ISL22326
Description
Manufacturer
Intersil Corporation
Datasheet

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Part Number:
ISL22326UFV14Z
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Intersil
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Part Number:
ISL22326UFV14Z-TK
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Intersil
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ISL22326WFR16Z-TK
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ISL22326WFV14Z-TK
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ISL22326WMVEP
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Low Noise, Low Power, I
128 Taps
The ISL22326 integrates two digitally controlled
potentiometers (XDCP) and non-volatile memory on a
monolithic CMOS integrated circuit.
The digitally controlled potentiometers are implemented with
a combination of resistor elements and CMOS switches. The
position of the wipers are controlled by the user through the
I
volatile Wiper Register (WR) and a non-volatile Initial Value
Register (IVR) that can be directly written to and read by the
user. The contents of the WR controls the position of the
wiper. At power-up the device recalls the contents of the two
DCP’s IVR to the corresponding WRs.
The DCPs can be used as three-terminal potentiometers or
as two-terminal variable resistors in a wide variety of
applications including control, parameter adjustments, and
signal processing.
Pinout
Ordering Information
NOTES:
ISL22326UFV14Z
(Notes 1, 2)
ISL22326WFV14Z
(Notes 1, 2)
2
1. Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
2. Add “-TK” suffix for 1,000 Tape and Reel option
C bus interface. Each potentiometer has an associated
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are
MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
PART NUMBER
SHDN
RW0
RH0
SCL
V
RL0
CC
A2
(14 LD TSSOP)
1
2
3
4
5
6
7
TOP VIEW
ISL22326
22326 UFVZ
22326 WFVZ
®
PART MARKING
1
2
Data Sheet
C
14
13
12
10
11
9
8
®
Bus,
A1
A0
RH1
RL1
RW1
GND
SDA
1-888-INTERSIL or 1-888-468-3774
RESISTANCE OPTION
Dual Digitally Controlled Potentiometers (XDCP™)
(kΩ)
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
50
10
Features
• Two potentiometers in one package
• 128 resistor taps
• I
• Non-volatile storage of wiper position
• Wiper resistance: 70Ω typical @ 3.3V
• Shutdown mode
• Shutdown current 5µA max
• Power supply: 2.7V to 5.5V
• 50kΩ or 10kΩ total resistance
• High reliability
• 14 Ld TSSOP
• Pb-free plus anneal product (RoHS compliant)
|
- Three address pins, up to eight devices/bus
- Endurance: 1,000,000 data changes per bit per register
- Register data retention: 50 years @ T <55
2
Intersil (and design) and XDCP are registered trademarks of Intersil Americas Inc.
C serial interface
TEMP. RANGE
-40 to +125
-40 to +125
All other trademarks mentioned are the property of their respective owners.
July 17, 2006
(°C)
Copyright Intersil Americas Inc. 2006. All Rights Reserved
14 Ld TSSOP
(Pb-free)
14 Ld TSSOP
(Pb-free)
PACKAGE
ISL22326
M14.173
M14.173
PKG. DWG. #
°
FN6176.0
C

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ISL22326 Summary of contents

Page 1

... Low Noise, Low Power 128 Taps The ISL22326 integrates two digitally controlled potentiometers (XDCP) and non-volatile memory on a monolithic CMOS integrated circuit. The digitally controlled potentiometers are implemented with a combination of resistor elements and CMOS switches. The position of the wipers are controlled by the user through the ...

Page 2

... A2 7 SCL 8 SDA 9 GND 10 RW1 11 RL1 12 RH1 ISL22326 V CC POWER-UP INTERFACE CONTROL AND STATUS LOGIC NON- VOLATILE REGISTERS GND Power supply pin Shutdown active low input “High” terminal of DCP0 “Low” terminal of DCP0 “Wiper” terminal of DCP0 ...

Page 3

... FSerror Full-scale Error (Note 8) V DCP to DCP Matching MATCH (Note 11) TC Ratiometric Temperature Coefficient V (Note 12) 3 ISL22326 Thermal Information Thermal Resistance (Typical, Note 3) 14 Lead TSSOP package . . . . . . . . . . . . . . . . . . . . +0.3 CC Recommended Operating Conditions CC Temperature Range (Extended Industrial .-40°C to +125° 2.7V to 5.5V CC Power Rating of each DCP . . . . . . . . . . . . . . . . . . . . . . . . . . . .5mW Wiper Current of each DCP . . . . . . . . . . . . . . . . . . . . . . . . . . ± ...

Page 4

... Vpor Power-on Recall Voltage VccRamp V Ramp Rate CC t Power-up Delay D 4 ISL22326 TEST CONDITIONS i and R i with R i not connected, or between DCP register set between 10h and 7Fh; monotonic over all tap positions DCP register set between 10h and 7Fh; ...

Page 5

... R t SDA and SCL Fall Time F Cb Capacitive Loading of SDA or SCL Rpu SDA and SCL Bus Pull-up Resistor Off-chip 5 ISL22326 TEST CONDITIONS T <55 Temperature °C Any pulse narrower than the max spec is suppressed SCL falling edge crossing 30 until CC SDA exits the 30 ...

Page 6

... HD:STA SDA (INPUT TIMING) SDA (OUTPUT TIMING) A0, A1, and A2 Pin Timing START SCL SDA A0, A1 ISL22326 TEST CONDITIONS Before START condition After STOP condition ) and V(R ) are V(R ) for the DCP register set to 7F hex and 00 hex respectively. LSB is the 127 ...

Page 7

... TAP POSITION (DECIMAL) FIGURE 3. DNL vs TAP POSITION IN VOLTAGE DIVIDER MODE FOR 10kΩ (W) 1.30 10k 1.10 0.90 0.70 0.50 Vcc = 5.5V 0.30 0.10 50k -0.10 -0.30 -40 - TEMPERATURE (ºC) FIGURE 5. ZSerror vs TEMPERATURE 7 ISL22326 1.4 1.2 1 0.8 0.6 0.4 Vcc = 3.3V -40ºC 0 100 120 2.7 0 25ºC 0.1 0 -0.1 -0.2 80 100 120 FIGURE 4. INL vs TAP POSITION IN VOLTAGE DIVIDER ...

Page 8

... TEMPERATURE (ºC) FIGURE 9. END TO END R % CHANGE vs TOTAL TEMPERATURE 300 250 10k 200 150 100 TAP POSITION (DECIMAL) FIGURE 11. TC FOR Rheostat MODE IN ppm 8 ISL22326 (Continued) 0.4 0.2 -0.2 -0.4 -0.6 96 116 FIGURE 8. INL vs TAP POSITION IN Rheostat MODE FOR 105 50k 10k 15 60 ...

Page 9

... Pin Descriptions Potentiometers Pins RHi and RLi ( The high (RHi) and low (RLi) terminals of the ISL22326 are equivalent to the fixed terminals of a mechanical potentiometer. RHi and RLi are referenced to the relative position of the wiper and not the voltage potential on the terminals ...

Page 10

... Protocol Conventions Data states on the SDA line must change only during SCL LOW periods. SDA state changes during SCL HIGH are reserved for indicating START and STOP conditions (See Figure 16). On power-up of the ISL22326 the SDA pin is in the input mode. 2 All I ...

Page 11

... During the ninth clock cycle, the receiver pulls the SDA line LOW to acknowledge the reception of the eight bits of data (See Figure 17). The ISL22326 responds with an ACK after recognition of a START condition followed by a valid Identification Byte, and once again after successful receipt of an Address Byte. The ISL22326 also responds with an ACK after receiving a Data Byte of a write operation ...

Page 12

... Identification Byte, a valid Address Byte, a Data Byte, and a STOP condition. After each of the three bytes, the ISL22326 responds with an ACK. At this time, the device enters its standby state (See Figure 18). Device can receive more than one byte of data by auto incrementing the address after each received byte. Note after reaching the address 08h, the internal pointer “ ...

Page 13

... However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 13 ISL22326 M14.173 14 LEAD THIN SHRINK SMALL OUTLINE PLASTIC M ...

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