ISL54225 Intersil, ISL54225 Datasheet
ISL54225
Available stocks
Related parts for ISL54225
ISL54225 Summary of contents
Page 1
... USB transceivers. The digital logic inputs are 1.8V logic compatible when operated with a 2.7V to 3.6V supply. The ISL54225 has an output enable pin to open all the switches. It can be used to facilitate proper bus disconnect and connection when switching between the USB sources ...
Page 2
... Logic “0” when ≤ 0.5V, Logic “1” when ≥ 1.4V with a 2.7V to 3.6V Supply. Note: In Low Power mode there is no persistence checking when in OVP condition. ) COMs SHORTED TO DD VBUS -5V www.DataSheet4U.com ISL54225 (10 LD 3X3 TDFN) TOP VIEW PD LOGIC 1 10 CONTROL ...
Page 3
... SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 5. For Moisture Sensitivity Level (MSL), please see device information page for ISL54225. For more information on MSL please see techbrief TB363. ...
Page 4
... V = 3.3V, 0.3V, V HSD2x(OFF 3.3V, 0.3V HSD1X 4 ISL54225 Thermal Information Thermal Resistance (Typical µTQFN Package (Note TDFN Package (Notes 8, 9). . Maximum Junction Temperature (Plastic Package). . Maximum Storage Temperature Range . . . -65°C to +150°C Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp Recommended Operating Conditions Temperature Range . . . . . . . . . . . . . . . . . . -40° ...
Page 5
... Signal = 0dBm, 0.2VDC offset, R OFF Capacitance 1MHz, V HSxOFF COM ON Capacitance 1MHz (see Figure 4) DX(ON) 5 ISL54225 Test Conditions 0.5V, V SELL Otherwise Specified. Boldface limits apply over the operating temperature range, -40°C to +85°C. (Continued) TEST CONDITIONS , 0.3V ...
Page 6
... ON lowest max r value, between HSD2+ and HSD2- or between HSD1+ and HSD1-. ON 15. Limits established by characterization and are not production tested. 6 ISL54225 Test Conditions 0.5V, V SELL Otherwise Specified. Boldface limits apply over the operating temperature range, -40°C to +85°C. (Continued) ...
Page 7
... Logic input waveform is inverted for switches that have the opposite logic sense. FIGURE 1A. MEASUREMENT POINTS VDD LOGIC INPUT 0V SWITCH OUTPUT V OUT 0V FIGURE 2A. MEASUREMENT POINTS V Repeat test for all switches. 7 ISL54225 t < 20ns r t < 20ns f SWITCH INPUT V OUT 90% Repeat test for all switches. C capacitance. FIGURE 1. SWITCHING TIMES V ...
Page 8
... OUT+ t skew_o OUT- 50% 90% 10 FIGURE 6A. MEASUREMENT POINTS 8 ISL54225 (Continued) VDD C SIGNAL GENERATOR SEL 0V OR VDD OE ANALYZER Signal direction through switch is reversed, worst case values are recorded. Repeat test for all switches. FIGURE 5. CROSSTALK TEST CIRCUIT VIN 15.8Ω DIN+ 15.8Ω ...
Page 9
... GND Detailed Description The ISL54225 device is a dual single pole/double throw (SPDT) analog switch configured as a DPDT that operates from a single DC power supply in the range of 2.7V to 5.25V. It was designed to function as a dual 2-to-1 multiplexer to select between two USB high-speed differential data signals in portable battery powered products offered in a TDFN, and a small µ ...
Page 10
... USB 5V V shorted to one or both of the COM+ and COM- pins or a negative voltage < -0.5V (typ) to -5V gets shorted to one or both of the COM pins, the ISL54225 has OVP circuitry to detect the overvoltage condition and open the SPDT switches to prevent damage to the USB down-stream transceivers connected at the signal pins (HS1D-, HS1D+, HS2D-, HS2D+) ...
Page 11
... LOGIC CONTROL The state of the ISL54225 device is determined by the voltage at the SEL pin and the OE pin. SEL is only active when the OE pin is logic “0” (Low). Refer to “Truth Table” on page 2. The ISL54225 logic pins are designed to minimize current consumption when the logic control voltage is lower than the V supply voltage ...
Page 12
... COM FIGURE 11. ON-RESISTANCE vs SUPPLY VOLTAGE vs SWITCH VOLTAGE 3.3V DD +85° 17mA COM 7 +25° -40° 0.1 0.2 V (V) COM FIGURE 13. ON-RESISTANCE vs SWITCH VOLTAGE 12 ISL54225 T = +25°C, Unless Otherwise Specified 0.3 0.4 0 FIGURE 10. ON-RESISTANCE vs SUPPLY VOLTAGE 3.6V 6 5.25V 4. 2.4 3.0 3.6 0 FIGURE 12 ...
Page 13
... OE = “0” (NORMAL OPERATION “1” (LOW POWER - LOGIC VOLTAGE (V) FIGURE 19. IDD vs SEL LOGIC VOLTAGE vs OE STATE 13 ISL54225 T = +25°C, Unless Otherwise Specified (Continued +25°C 2.4 3.0 3.6 FIGURE 16. ON-RESISTANCE vs SWITCH VOLTAGE 350 300 250 200 150 ...
Page 14
... Typical Performance Curves V = 3.3V DD FIGURE 21. EYE PATTERN: 480Mbps WITH USB SWITCHES IN THE SIGNAL PATH FIGURE 22. EYE PATTERN: 12Mbps WITH USB SWITCHES IN THE SIGNAL PATH 14 ISL54225 T = +25°C, Unless Otherwise Specified (Continued) A TIME SCALE (0.2ns/DIV) TIME SCALE (10ns/DIV) www.DataSheet4U.com V = 3.3V DD FN7627.0 July 2, 2010 ...
Page 15
... 0dBm, 0.2VDC BIAS -20 IN -30 -40 -50 -60 -70 -80 -90 -100 -110 0.001 0.01 0.1 1 FREQUENCY (MHz) FIGURE 25. CROSSTALK 15 ISL54225 T = +25°C, Unless Otherwise Specified (Continued) A -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 0.001 100M 1G Die Characteristics SUBSTRATE AND TDFN THERMAL PAD POTENTIAL (POWERED UP): ...
Page 16
... No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see 16 ISL54225 for a complete list of Intersil product families. ISL54225 www.intersil.com/askourstaff http://rel.intersil.com/reports/search.php www.intersil.com/product_tree www.intersil.com/design/quality www.DataSheet4U.com CHANGE www ...
Page 17
... Package Outline Drawing L10.1.8x1.4A 10 LEAD ULTRA THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 5, 3/10 1. 0.10 2X TOP VIEW (9 X 0.60) (10X 0.20) 3 (4X 0.30 TYPICAL RECOMMENDED LAND PATTERN 17 ISL54225 6 A PIN #1 ID 0.50 6 PIN 1 INDEX AREA 0.70 MAX. 0. (0.70) (0.70) 8 PACKAGE OUTLINE (6X 0.40) NOTES: 1. Dimensions are in millimeters. ...
Page 18
... Package Outline Drawing L10.3x3A 10 LEAD THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE Rev 5, 3/10 3.00 B 3.00 TOP VIEW ( 2.30 ) (2.90 .50 ) TYPICAL RECOMMENDED LAND PATTERN 18 ISL54225 6 A PIN 1 INDEX AREA 6 PIN 1 INDEX AREA 0.15 (4X) 0 .80 MAX (1.50) (10 X 0.50) ( 10X 0.25 ) NOTES: 1. Dimensions are in millimeters. Dimensions Dimensioning and tolerancing conform to ASME Y14.5m-1994. ...