ISL59530 Intersil Corporation, ISL59530 Datasheet
ISL59530
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ISL59530 Summary of contents
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... The ISL59530 interface is designed to facilitate both fast updates and initialization. On power-up, all outputs are high impedance to avoid output conflicts. The ISL59530 is available in a 356 ball BGA package and specified over an extended -40°C to +85°C temperature range. The single-supply ISL59530 can accommodate input signals from ...
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... W Y In3 In2 BALLS Balls labelled “NC” should be left unconnected - do not tie them to ground! Balls with no labels may be tied to ground to slightly reduce thermal impedance. 2 ISL59530 ISL59530 (356 LD BGA) TOP VIEW In15 Over15 Out15 Vover15 ...
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... Glitch Switching Glitch, Peak T Overlay Delay Time over dG Diff Gain dP Diff Phase Xt Hostile Crosstalk V Input Referred Noise Voltage N 3 ISL59530 = +25°C) Maximum power supply (V ESD Classification Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1500V Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100V = 5V 150Ω unless otherwise noted ...
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... Never let the VREF pin float! A float- ing VREF pin drifts high (and if the clamp function is enabled) will cause all of the outputs to simultaneously try to drive ~4V DC into their 150 SLATCH J3 Serial Latch. Serial data is latched into ISL59530 on rising edge of SLATCH. DESCRIPTION Ω loads. FN6220.1 June 12, 2006 ...
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... K3 Serial data clock SDI L3 Serial data input SDO G3 Serial data output. Can be tied to SDI of another ISL59530 to enable daisy- chaining of multiple devices. RESET H3 Reset input. Pull high then low to reset device, but not needed in normal opera- tion. Tie to ground in final application Power supply for SDO pin ...
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... Overlay mode 100Ω =0pF L INPUT_CH 0 OUTPUT_CH 15 FIGURE 5. FREQUENCY RESPONSE - OVERLAY INPUT ISL59530 10pF 0pF , FIGURE 2. FREQUENCY RESPONSE - VARIOUS 50Ω FIGURE 4. FREQUENCY RESPONSE - VARIOUS FIGURE 6. FREQUENCY RESPONSE - OVERLAY INPUT, 15pF V =+5V ...
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... FIGURE 9A. FREQUENCY RESPONSE - VARIOUS R BROADCAST MODE ADJACENT 100Ω INPUT_CH14 OUTPUT_CH15 L FIGURE 11. CROSSTALK - A 7 ISL59530 (Continued) 0pF , FIGURE 8. FREQUENCY RESPONSE - VARIOUS 50Ω FIGURE 10. FREQUENCY RESPONSE - VARIOUS ALL HOSTILE INPUT_CH0 OUTPUT_CH15 = 1 ...
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... Typical Performance Curves THD 2nd HD 3rd HD FIGURE 13. HARMONIC DISTORTION vs FREQUENCY FIGURE 15. DISABLED OUTPUT IMPEDANCE MUX MODE 100Ω L INPUT_CH 0 OUTPUT_CH 0 TIME (ns) FIGURE 17. RISE TIME - A 8 ISL59530 (Continued =100Ω L INPUT_CH 1 OUTPUT_CH 1 V =2V OP-P FIGURE 14. HARMONIC DISTORTION vs V RISE TIME 2 ...
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... INPUT_CH 0 OUTPUT_CH 0 TIME (ns) FIGURE 21. RISING SLEW RATE - A MUX MODE =100Ω L INPUT_CH 0 OUTPUT_CH 0 TIME (ns) FIGURE 23. RISING SLEW RATE - A 9 ISL59530 (Continued) RISE TIME 2.32ns = 2 V SLEW RATE 405V/µ SLEW RATE 430V/µ FALL TIME 2.40ns MUX MODE ...
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... R = 100Ω L INPUT_CH 1 OUTPUT_CH 1 OSC = 40mV FIGURE 27. DIFFERENTIAL GAIN 100Ω L INPUT_CH 1 OUTPUT_CH 1 OSC = 40mV FIGURE 29. DIFFERENTIAL GAIN ISL59530 (Continued) OVERLAY LOGIC INPUT FIGURE 26. OVERLAY SWITCH TURN-OFF DELAY TIME = OUTPUT OVERLAY LOGIC INPUT 100Ω ...
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... 100Ω L INPUT_CH 1 OUTPUT_CH 1 OSC = 40mV FIGURE 33. DIFFERENTIAL GAIN 100Ω L INPUT_CH 01 OUTPUT_CH 15 OSC = 40mV FIGURE 35. DIFFERENTIAL GAIN ISL59530 (Continued 100Ω L INPUT_CH 1 OUTPUT_CH 1 OSC = 40mV FIGURE 32. DIFFERENTIAL PHASE 100Ω ...
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... 100Ω L INPUT_CH 01 OUTPUT_CH 15 OSC = 40mV FIGURE 39. DIFFERENTIAL GAIN 100Ω L INPUT_CH 01 OUTPUT_CH 15 OSC = 40mV FIGURE 41. DIFFERENTIAL GAIN ISL59530 (Continued 100Ω L INPUT_CH 01 OUTPUT_CH 15 OSC = 40mV FIGURE 38. DIFFERENTIAL PHASE 100Ω ...
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... L INPUT_CH 01 OUTPUT_CH 01 OSC = 40mV FIGURE 43. DIFFERENTIAL GAIN, OVERLAY 100Ω L INPUT_CH 01 OUTPUT_CH 01 OSC = 40mV FIGURE 45. DIFFERENTIAL GAIN, OVERLAY ISL59530 (Continued FIGURE 44. DIFFERENTIAL PHASE, OVERLAY FIGURE 46. DIFFERENTIAL PHASE, OVERLAY 100Ω L INPUT_CH 01 OUTPUT_CH 01 OSC = 40mV ...
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... ISL59530 = 100 Ω [MHz] L INPUT CHANNELS 224 190 169 152 233 190 212 180 168 186 171 183 175 ...
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... ISL59530 = 100 Ω [MHz INPUT CHANNELS 172 178 151 145 157 145 140 146 174 152 171 ...
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... Timing Diagram). After all 16 bits of data have been loaded into the shift register, the rising edge of SLATCH updates the internal registers. While the ISL59530 has an SDO (Serial Data Out) pin, it does not have a register readback feature. The data on the SDO pin is an exact replica of the incoming data on the SDI pin, delayed by 15 ...
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... RECOMMENDED OPERATING RANGE Programming Model The ISL59530 is configured by a series of 16 bit serial control words. The three MSBs (B15-13) of each serial word determine the basic command: B15 B14 B13 INPUT/OUTPUT: Maps input channels to output channels ...
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... Broadcast Mode disable Broadcast Mode. When Broadcast Mode is disabled, the previous channel assignments are restored. Control Word The ISL59530’s power-on reset disables all outputs and places the part in a low-power standby mode. To enable the device, the following control word should be sent: B15 B14 B13 B12 B11 B10 ...
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... ISL59530 should be configured to operate in its most linear operating region. Figure 48 shows the differential gain curve. The ISL59530 is a single supply 5V design with its most linear region between 0.1 and 2V. This range is fine for most video signals whose nominal signal amplitude is 1V. ...
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... V source some current into C1 to make V the sync tip. This is how the video is “DC-restored” after being AC coupled into the ISL59530. The sync tip voltage will be equal the right side regardless of the DC level ...
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... However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 21 ISL59530 C ° C ° ...
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Ld PBGA Package ...