ISL6112 INTERSIL [Intersil Corporation], ISL6112 Datasheet
ISL6112
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ISL6112 Summary of contents
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... Data Sheet Dual Slot PCI-Express Power Controller The ISL6112 targets the PCI-Express add-in card hot plug application. Together with two each of N-Channel and P-Channel MOSFETs, four current sense resistors and several external passive components the ISL6112 provides a compliant hot plug power control solution to any combination of two PCI-Express X1, X4 X16 slots ...
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... ON/OFF 100mV* ON/OFF 100mV* VSTBY I REF CFILTER 1.25V FORCE_ON GPI BOTH A AND B SLOTS SHARE THE SCL, SDA, A0, A1, A2, INT PINS. 2 ISL6112 ON AUXEN VSTBY POWER-ON VSTBY RESET UVLO 250µs 12V UVLO 3V UVLO ON/ OFF LOGIC CIRCUITS DIGITAL CORE/SERIAL INTERFACE ...
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... ISL6112 (48 LD 7X7 QFN) TOP VIEW FAULTA GPI_A0 5 12VINA GND (EXPOSED BOTTOM PAD 3VINA ...
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... VSTBYA, VSTBYB 3.3V Standby Input Voltage: Required to support PCI Express VAUX output. Additionally, the SMBus logic and internal registers run off of VSTBY to ensure that the chip is accessible during standby modes. A UVLO circuit prevents turn-on of this supply until VSTBY rises above its UVLO threshold. Both pins must be externally connected together at the ISL6112 controller. 15, 22 VAUXA, VAUXB 3.3VAUX Outputs to PCI Express Card Slots: These outputs connect the 3.3AUX pin of the PCI Express connectors to VSTBY via internal 400mΩ ...
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... IC Reference pins. Connect together and tie directly to the system’s analog GND plane directly at the device. 7, 18, 19, 20 Reserved: Make no external connections to these pins. 5 ISL6112 (Continued) PIN FUNCTION . Bringing the slot’s ON pin low resets FAULT if FAULT was asserted in response to a STBY FN6456.0 ...
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... Voltage 3VGATE Charge Current (3VCHARGE) 3VGATE Sink Current (Fault Off) IGATE(3VSINK) 6 ISL6112 ) Thermal Information Thermal Resistance (Typical 7x7 TQFP Package (Note 7x7 QFN Package (Notes Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +150°C Maximum Storage Temperature Range . . . . . . . . . -65°C to +150°C Pb-free reflow profile ...
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... Delay from MAIN Overcurrent to FAULT Output (12V FAULT or 3V Delay from VAUX Overcurrent to FAULT Output (VAUXFAULT) ON, AUXEN, PRSNT Minimum Pulse Width Power-On Reset Time after VSTBY Becomes Valid 7 ISL6112 = T A SYMBOL CONDITION VFILTER IFILTER VXVIN – VXSENSE > VTHILIMIT tFILTER CFILTER Open VTHILIMIT VXIN – ...
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... SCL (clock) period Data In setup time to SCL HIGH Data Out stable after SCL LOW Data LOW setup time to SCL LOW Data HIGH hold time after SCL HIGH NOTE: 5. Limits established by design and are not production tested. 8 ISL6112 = SYMBOL CONDITION t1 (Note 5) ...
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... INT 33 47 GND SCL 46 48 GND SDA SDA MANAGEMENT SCL CONTROLLER INT * Values for R # These components are not required for ISL6112 • Bold lines indicate high current paths ^ R PCI-EXPRESS CONNECTOR PCI EXPRESS 0.1µF BUS 3.3AUX RSENSE^ 375mA *R12VGATEA 15Ω 12V 2.1A (x4/x8) 0.1µF RSENSE^ 0.015Ω ...
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... SMI or HPI, or can employ the HPl for power control while continuing to use the SMI for access to all but the power control registers. In addition to the basic power control features of the ISL6112 accessible by the HPI, the SMI also gives the host access to the following information from the part: • ...
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... When a slot's MAIN supplies are off, the 12VGATE pin is held high with an internal pull-up to the 12VIN voltage. Similarly, the 3VGATE pin is internally held low to GND. When the MAIN supplies of the ISL6112 are enabled by asserting ON, the related 3VGATE and 12VGATE pins are each connected to a constant current supply. For the 3VGATE pin, this is nominally a 25µ ...
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... In some scope shots although the C FILTER in the absence of excessive displayed loading current the C is responding to the other MAIN supply current that FILTER is not displayed. All scope shots were taken from the ISL6112EVAL1Z with any component changes noted. 12 ISL6112 is the load FILTER, ] until the ...
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... LOAD C = 470µF LOAD Current Regulation (CR) Function The ISL6112 provides a current regulation and limiting function that protects the input voltage supplies against excessive loads, including short circuits. When the current from any of a slots MAIN outputs exceeds the current limit threshold (I ...
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... See Figures 12 and 13 for illustrations of the VAUX protection performance into a slight OC and more severe OC condition respectively. The ISL6112 AUX current control responds proportionally to the severity of the OC condition resulting in faster VAUX pull-down and current regulation until t has expired ...
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... VSTBY using an external pull-up resistor or simply shorted to VSTBY. General Purpose Input (GPI) Pins Two pins on the ISL6112 are available for use as GPI pins. The logic state of each of these pins can be determined by polling Bits [4:5] of Common Status Register. Both of these inputs are compliant to 3 ...
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... FIGURE 16. HOT-PLUG INTERFACE OPERATION COMMAND BYTE TO ISL6112 R/W = WRITE ACKNOWLEDGE ACKNOWLEDGE MASTER TO DEVICE TRANSFER, DEVICE TO MASTER TRANSFER, i.e., DATA DRIVEN BY MASTER. i.e., DATA DRIVEN BY DEVICE. FIGURE 17. WRITE_BYTE PROTOCOL VIH VIL tFLT * DATA BYTE TO ISL6112 ACKNOWLEDGE FN6456.0 September 28, 2007 ...
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... Once the input supplies are above their respective UVLO thresholds, the Hot-Plug Interface can be utilized for power control by enabling the control input pins (AUXEN and ON) for each slot. In order for the ISL6112 to switch on the VAUX supply for either slot, the AUXEN control must be enabled after the power-on-reset delay, t (typically, 250µ ...
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... ISL6112), then the “Receive_Byte” procedure may be used. To perform a Receive_Byte operation, the host sends an address byte to select the target ISL6112, with the R/W bit set to the high (read) state, and then retrieves the data byte. Figures 17 ...
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... ISL6112 Register Set and Programmer’s Model TARGET REGISTER LABEL CNTRLA Control Register Slot A CNTRLB Control Register Slot B STATA Slot A Status STATB Slot B Status CS Common Status Register Reserved Reserved/Do Not Use Detailed Register Descriptions Control Register, Slot A (CNTRLA) 8-Bits, Read/Write D[7] D[6] read-only ...
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... MAIN output and the VAUX output of slot A, both ONA and AUXENA of the slot must go low to reset FAULTA. 9. Neither the FAULTA bits nor the FAULTA pins are active when the ISL6112 power paths are controlled by the System Management Interface. When using SMI power path control, AUXENA and ONA pins for that slot must be tied to GND. ...
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... Not Good”) state. 12. The values of the MAINBPG and AUXBPG register bits are not affected by FORCE_ONB, but will instead continue to read as high if power is “Good,” and as low if the conditions, which indicate that power is good, are not met. 21 ISL6112 TABLE 7. CONTROL REGISTER, SLOT B (CNTRLB) D[5] D[4] ...
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... MAIN output and the VAUX output of slot B, both ONB and AUXENB of the slot must go low to reset FAULTB. 14. Neither the FAULTB bits nor the FAULTB pins are active when the ISL6112 power paths are controlled by the System Management Interface. When using SMI power path control, the AUXENB and ONB pins for that slot must be tied to GND. ...
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... This bit is only set if a UVLO condition occurs while the ON pin is asserted or the MAIN control bits are set 0 = Die Temp < +160° Fault: Die Temp > +160°C. Set if a fault occurs as a result of the ISL6112’s die temperature exceeding +160°C Undefined D[0] read-only Reserved FN6456 ...
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... AUX supply power. For each of the slots a 7mΩ sense resistor provides a nominal CR level of 7.1A, 14% above the 6.25A max spec. The ISL6112 provides a best in class ±5% current regulation threshold spec over temperature for the MAIN supples providing the highest accuracy and lowest variability for this critical parameter ...
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... TEMPERATURE (°C) FIGURE 22. CURRENT LIMIT THRESHOLD VOLTAGE vs TEMPERATURE 1200 1150 1100 1050 1000 950 900 850 800 -60 -40 - TEMPERATURE (°C) FIGURE 24. AUX. CURRENT LIMIT vs TEMPERATURE 25 ISL6112 1.0 0.8 0.6 0.4 0 100 120 104 103 102 101 100 100 120 FIGURE 23 ...
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... TEMPERATURE (°C) FIGURE 28. 12MAIN POWER GOOD THRESHOLD VOLTAGE vs TEMPERATURE 25.5 25.0 3VGATE 24.5 24.0 23.5 12VGATE 23.0 22.5 22.0 -60 -40 - TEMPERATURE (°C) FIGURE 30. ISL6112 GATE TURN-ON CURRENT (ABS) vs TEMPERATURE 26 ISL6112 (Continued) 3.1 2.9 2.7 2.5 2.3 2.1 1.9 1.7 1 100 120 -60 FIGURE 27. AUX AND 3.3MAIN RISING UVLO THRESHOLD 2.80 2.79 2.78 2.77 2.76 2.75 2.74 2.73 2.72 2.71 2. 100 120 FIGURE 29 ...
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... Typical Performance Curves 3.0 2.9 2.8 2.7 2.6 2.5 2.4 2.3 2.2 2.1 2.0 -60 -40 - TEMPERATURE (°C) FIGURE 32. FILTER CHARGE CURRENT vs TEMPERATURE 27 ISL6112 (Continued) 1.30 1.28 1.26 1.24 1.22 1. 100 120 FIGURE 33. FILTER THRESHOLD VOLTAGE vs TEMPERATURE -60 -40 - TEMPERATURE (°C) 80 100 120 FN6456.0 September 28, 2007 ...
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... CAUTION HOT TABLE 11. ISL6112EVAL1Z BOARD COMPONENTS LISTING COMPONENT DESIGNATOR U1 Q1, Q4 Q2, Q3 R1, R3, R6, R8 R9, R10, R17, R20 R11, R12, R13, 14, R15, R16, R18, 19, R21 R2, R4, R5, R7 C1, C7, C8, C13 C3, C5, C6, C10, C11, C14 C2, C12 C4, C9 R24, R25 C17, C18 R22, R26, R28, 29 ...
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... L48.7x7 48 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 4, 10/06 7.00 6 PIN 1 INDEX AREA (4X) 0.15 TOP VIEW ( TYP ) ( TYPICAL RECOMMENDED LAND PATTERN 30 ISL6112 4X 5.5 A 44X 0. 48X 0 . 40± BOTTOM VIEW ± SIDE VIEW ( 44X REF C ( 48X 0 ...
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... However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 31 ISL6112 Q48.7x7 48 LEAD THIN PLASTIC QUAD FLATPACK PACKAGE SYMBOL ...