ISL61851EVAL1Z Intersil, ISL61851EVAL1Z Datasheet

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... CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. | 1-888-INTERSIL or 1-888-468-3774 Intersil (and design registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2010. All Rights Reserved All other trademarks mentioned are the property of their respective owners. DS(ON) ...

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Simplified Block Diagram GND VIN EN_1 EN_2 Ordering Information PART NUMBER PART (Notes MARKING ISL61851ACBZ 61851A CBZ ISL61851BCBZ 61851B CBZ ISL61851CCBZ 61851C CBZ ISL61851DCBZ 61851D CBZ ISL61851ECBZ 61851E CBZ ISL61851FCBZ 61851F CBZ ISL61851GCBZ 61851G CBZ ISL61851HCBZ 61851H ...

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Ordering Information PART NUMBER PART (Notes MARKING ISL61852GCRZ 52GC ISL61852HCRZ 52HC ISL61852ICRZ 52IC ISL61852JCRZ 52JC ISL61852KCRZ 52KC ISL61852LCRZ 52LC ISL61853ACRZ 53AC ISL61853BCRZ 53BC ISL61853CCRZ 53CC ISL61853DCRZ 53DC ISL61853ECRZ 53EC ISL61853FCRZ 53FC ISL61853GCRZ 53GC ISL61853HCRZ 53HC ISL61853ICRZ 53IC ...

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... ISL61853MIRZ 53MI ISL61853NIRZ 53NI ISL61853OIRZ 53OI ISL61853PIRZ 53PI ISL61851EVAL1Z 8 Lead SOIC Evaluation Platform ISL61852EVAL1Z 8 Lead DFN Evaluation Platform ISL61853EVAL1Z 10 Lead DFN Evaluation Platform NOTES: 1. Add “-T*” suffix for tape and reel. Please refer to 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations) ...

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Pin Configurations ISL6185 (8 LD SOIC/DFN) TOP VIEW GND 1 (GND) VIN 2 EPAD DFN Only 3 EN1/EN1 4 EN2/EN2 Pin Descriptions PIN NUMBER SOIC/DFN DFN SYMBOL 1 1 GND VIN 3, 4, ...

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... Lead SOIC Package (Note Lead 3x3 DFN Package (Notes Lead 3x3 DFN Package (Notes Maximum Junction Temperature . . . . . . . . . . . . . . +150°C Maximum Storage Temperature Range . . . . -65°C to +150°C Pb-Free Reflow Profile see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp = 5V Unless Otherwise Specified. Boldface limits apply over the operating IN A ...

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Electrical Specifications V temperature range, 0°C to +75°C or -40°C to +85°C. (Continued) SYMBOL PARAMETER I Maximum Continuous Current, OUT_CONT_2 OUT_CONT_2 I OUT_CONT_2 I OUT_CONT_2 I OUT_CONT_2 I Trip Current TRIP_5 IN ...

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Electrical Specifications V temperature range, 0°C to +75°C or -40°C to +85°C. (Continued) SYMBOL PARAMETER tsett OC to Limit Settling Time Ilim tsett Severe OC to Limit Settling Ilim_sev Time t Current Limit Duration CL t Automatic Retry Period RTY ...

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Introduction The ISL6185 is a dual channel fully independent overcurrent (OC) fault protection IC for the +2.5V to +5V environment. Each ISL6185 incorporates in a single package two 85mΩ P-channel MOSFET power switches for power control. Independent enabling inputs and ...

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Turn-off Time Delay During operation, once an OC condition is detected the output is current limited for ~12ms to allow transient OC conditions to pass. If still in current limit and after the current limit period has elapsed, the output ...

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Typical Performance Curves 2.0 1 TRIP 3.3V I TRIP 1.6 1.4 3.3V I LIM 1.2 1.0 0.8 -40 - TEMPERATURE (°C) FIGURE 5. 1.5A CONTINUOUS CURRENT CHARACTERISTICS 0.75 0.6A CONTINUOUS I OUT 0.70 0.65 0.60 ...

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Typical Performance Curves ENABLE C =1µF C =10µ =100µF L VOUT 1V/DIV FIGURE 11. V TURN-ON/RISE TIME vs C OUT 10Ω =10µ OUT C =100µF 1V/DIV L ...

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Typical Performance Curves ENABLE 0.6A I VARIANT CONT I IN LIMITED TO 0.64A FIGURE 17. TURN-ON INTO A SHORT FIGURE 19. ISL6185 RETRY FUNCTION ENABLE FAULT V OUT I 1. FIGURE 21 2.5V TURN-ON INTO 2.2Ω ...

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Typical Performance Curves ENABLE V OUT I IN LIMITED TO 1.7A FAULT 1.8A I VARIANT CONT FIGURE 23. TURN-ON INTO A SHORT FIGURE 25. ISL6185 RETRY FUNCTION FIGURE 26. PROPAGATION DELAY AND OUTPUT TRANSITION TIMES Test Circuits + 10k FLT ...

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... FIGURE 28A. TRANSIENT TEST CIRCUIT ISL6185xEVAL1Z Schematic and Photo R1 10k AGND AGND EN1 A ISL6185 EN2 10k NOTE: EXPOSED PAD only on DFN packages FIGURE 30A. ISL6185xEVAL SCHEMATIC FIGURE 30. ISL6185xEVAL1Z SCHEMATIC and ISL61851EVAL1Z PHOTOGRAPH 15 ISL6185 ISL6185 EN OUTPUT µ FIGURE 29. TRANSIENT WAVEFORM MEASUREMENT FLT1 OUT1 FLT1 OUT1 A 10µ ...

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... The evaluation platform is biased and monitored through numerous labeled test points. See Table 1 for test point assignments and descriptions. TABLE 1. ISL61851EVAL1Z TEST POINT ASSIGNMENTS TP NAME DESCRIPTION GND Eval Board and IC Gnd ...

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... Initial release. Products Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The Company's products address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks. Intersil's product families address power management and analog signal processing functions ...

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Package Outline Drawing L8.3x3J 8 LEAD DUAL FLAT NO-LEAD PLASTIC PACKAGE Rev 0 9/09 3.00 (4X) 0.15 6 PIN 1 INDEX AREA TOP VIEW ( 2. 1.95) (1.64) ( 2.80 ) PIN 1 (6x 0.65) TYPICAL RECOMMENDED LAND ...

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Package Outline Drawing L10.3x3 10 LEAD DUAL FLAT PACKAGE (DFN) Rev 6, 09/09 3.00 6 PIN 1 INDEX AREA (4X) 0.10 TOP VIEW PACKAGE (10 x 0.55) OUTLINE (10x 0.23) (8x 0.50) 1.60 TYPICAL RECOMMENDED LAND PATTERN 19 ISL6185 A ...

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... Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries ...