ISL6263 INTERSIL [Intersil Corporation], ISL6263 Datasheet
ISL6263
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ISL6263 Summary of contents
Page 1
... DEM is enabled whenever a Render Suspend state has been set on the VID inputs. Optionally, DEM can be enabled for all VID states by setting the FDE pin high. The ISL6263 has an audio filter that can be enabled in any Render Suspend state by pulling the AF_EN pin high. The audio ...
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... RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD- 020. 3. For Moisture Sensitivity Level (MSL), please see device information page for ISL6263. For more information on MSL please see techbrief TB363. 2 ISL6263 ...
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... UNDER VOLTAGE OVER VOLTAGE FAULT LATCH + − + Σ − + − + − + E/A − FB COMP VIN FIGURE 1. SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM OF THE ISL6263 PWM CONTROL DRIVER DIODE EMULATION AUDIBLE FREQUENCY SHOOT THROUGH FILTER PROTECTION SEVERE OVERVOLTAGE SOFT CROWBAR CONTROL DRIVER g V PWM ...
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... V CC_SNS V SS_SNS R C FSET FSET C COMP1 R C COMP COMP2 R C DIFF2 DIFF R DIFF1 FIGURE 2. ISL6263 GPU RENDER-CORE VOLTAGE REGULATOR SOLUTION WITH DCR CURRENT SENSING 4 ISL6263 R VDD VDD PVCC RBIAS VIN SOFT UGATE I2UA BOOT C BOOT PGOOD PHASE VID<0:4> VR_ON AF_EN LGATE ...
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... V CC_SNS V SS_SNS R C FSET FSET C COMP1 R C COMP COMP2 R C DIFF2 DIFF R DIFF1 FIGURE 3. ISL6263 GPU RENDER-CORE VOLTAGE REGULATOR SOLUTION WITH RESISTIVE CURRENT SENSING 5 ISL6263 R VDD VDD PVCC RBIAS VIN SOFT UGATE I2UA BOOT C BOOT PGOOD PHASE VID<0:4> VR_ON AF_EN LGATE ...
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... REGULATION Output Voltage Range VID Voltage Step System Accuracy PWM Nominal Frequency 6 ISL6263 Thermal Information Thermal Resistance (Typical, Notes 4, 5) θ QFN Package Junction Temperature Range .-55°C to +150°C Operating Temperature Range . . . . . . . . . . . . . . . .-10°C to +100°C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C Pb-Free Reflow Profile .see link below http://www ...
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... PGOOD Low Voltage PGOOD Leakage Current Overvoltage Threshold (VO - VSOFT) Severe Overvoltage Threshold OCSET Reference Current OCSET Voltage Threshold Offset Undervoltage Threshold (VSOFT - VO) CONTROL INPUTS VR_ON Input Low 7 ISL6263 = -10°C to +100°C, unless otherwise stated. All typical specifications A SYMBOL TEST CONDITIONS A V0 GBW C = 20pF ...
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... VDIFF (Pin 7) - Connects to the output of the VDIFF differential-summing amplifier. VSEN (Pin 8) - This is the V input of the processor CC_SNS socket Kelvin connection. Connects internally to one of two non-inverting inputs of the VDIFF differential-summing amplifier. 8 ISL6263 = -10°C to +100°C, unless otherwise stated. All typical specifications A SYMBOL TEST CONDITIONS V VR_ONH V AF_ENL ...
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... FDE (Pin 32 low logic state on this pin confines the availability of diode emulation mode to Render Suspend VID states only. A high logic state on this pin enables diode emulation for all VID states. 9 ISL6263 TABLE 1. FDE AND AF_EN STATE TABLE RENDER MODE FDE ...
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... ISL6263 has an error amplifier that allows the controller to maintain tight voltage regulation accuracy throughout the VID range from 0.41200V to 1.28750V. 10 ISL6263 Power-On Reset CCGFX The ISL6263 is disabled until the voltage at the VDD pin has increased above the rising VDD power-on reset (POR) V CCGFX VID0 (V) V ...
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... Processor Socket Kelvin Voltage Sensing The remote voltage sense input pins VSEN and RTN of the ISL6263 are to be terminated at the die of the GPU through connections that mate at the processor socket. (The signal names are Vcc_sense and Vss_sense respectively.) Kelvin 10µ ...
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... OCP threshold but below twice the OCP threshold is 120µs, which is eight counts at 15µs each. The ISL6263 will latch an OCP fault within 2µs for an overcurrent exceeding twice the OCP threshold to maximize protection against hard shorts. The ...
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... UGATE t t PDRU PDRL FIGURE 6. GATE DRIVER TIMING DIAGRAM Internal Bootstrap Diode The ISL6263 has an integrated boot-strap Schottky diode connected from the PVCC pin to the BOOT pin. Simply adding an external capacitor across the BOOT and PHASE pins completes the bootstrap circuit. 2.0 1.8 1.6 1 ...
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... COMP than the typical value encountered in a typical application. Static Droop Design Using DCR Sensing The ISL6263 has an internal differential amplifier to accurately regulate the voltage at the processor die. For DCR sensing, the process to compensate the DCR resistance variation takes several iterative steps. Figure 2 ...
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... FIGURE 8. EQUIVALENT MODEL FOR DROOP CIRCUIT USING INDUCTOR DCR CURRENT SENSING − OCP + + − FIGURE 9. EQUIVALENT MODEL FOR DROOP CIRCUIT USING DISCRETE RESISTOR CURRENT SENSING 15 ISL6263 R is 8mΩ per Intel IMVP-6+ specification and R droop typically 1kΩ. (EQ. 14) The effectiveness of the R coupling coefficient between the NTC thermistor and the inductor ...
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... CCGFX load transient. Figure 12 shows the transient response when C is too large. V takes too long to droop to its final N CCGFX value. 16 ISL6263 FIGURE 10. DESIRED LOAD TRANSIENT RESPONSE DRP2 after the system is DRP2 FIGURE 11. LOAD TRANSIENT RESPONSE WHEN – DRP1 (EQ ...
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... VSS pin. The VSS island should be located under the IC package along with the weak analog traces and components. The paddle on the bottom of the ISL6263 QFN package is not electrically connected to the IC however recommended to make a (EQ. 20) good thermal connection to the VSS island using several vias ...
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... R should be placed in close RBIAS I2UA proximity to the ISL6263 using a noise-free current return path to the VSS pin. All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use ...
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... Package Outline Drawing L32.5x5 32 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 3, 4/10 5.00 6 PIN 1 INDEX AREA (4X) 0.15 TOP VIEW ( 4. 80 TYP ) ( TYPICAL RECOMMENDED LAND PATTERN 19 ISL6263 ± 0.1 ( 28X (32X 32X 0 . 60) NOTES: 1. Dimensions are in millimeters. Dimensions ...