isl6322g Intersil Corporation, isl6322g Datasheet

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isl6322g

Manufacturer Part Number
isl6322g
Description
Two-phase Buck Pwm Controller With Integrated Mosfet Drivers, I 2c Interface, And Phase Dropping
Manufacturer
Intersil Corporation
Datasheet

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isl6322gIRZ
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Intersil
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Two-Phase Buck PWM Controller with
Integrated MOSFET Drivers, I
and Phase Dropping
The ISL6322G two-phase PWM control IC provides a
precision voltage regulation system for advanced
microprocessors and memory. The integration of power
MOSFET drivers into the controller IC marks a departure
from the separate PWM controller and driver configuration of
previous multiphase product families. By reducing the
number of external parts, this integration is optimized for a
cost and space saving power management solution.
One outstanding feature of this controller IC is its
multi-processor compatibility, allowing it to work with both Intel
and AMD microprocessors. Included are programmable VID
codes for Intel VR10, VR11, as well as AMD DAC tables. A
unity gain, differential amplifier is provided for remote voltage
sensing, compensating for any potential difference between
remote and local grounds. The output voltage can also be
positively or negatively offset through the use of a single
external resistor.
The ISL6322G includes an I
controller to communicate with other devices over an I
bus. Signals sent over this bus can command the ISL6322G
to adjust the number of active phases, voltage margining
offset, phase switching frequency, overvoltage protection
levels, and can select the integrated driver adaptive dead
time scheme.
The ISL6322G also includes advanced control loop features
for optimal transient response to load apply and removal.
One of these features is highly accurate, fully differential,
continuous DCR current sensing for channel-current
balance. Active Pulse Positioning (APP) modulation is
another unique feature, allowing for quicker initial response
to high di/dt load transients.
This controller also allows the user the flexibility to choose
between PHASE detect or LGATE detect adaptive dead time
schemes. This ability allows the ISL6322G to be used in a
multitude of applications where either scheme is required.
Protection features of this controller IC include a set of
sophisticated overvoltage, undervoltage, and overcurrent
protection. Furthermore, the ISL6322G includes protection
against an open circuit on the remote sensing inputs.
Combined, these features provide advanced protection for the
microprocessor and power system.
®
2
C interface, allowing the
1
Data Sheet
2
C Interface,
2
1-888-INTERSIL or 1-888-468-3774
C
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
Features
• Integrated Multiphase Power Conversion
• Phase Dropping for Higher Efficiency at Low Output
• Precision Core Voltage Regulation
• Optimal Transient Response
• Fully Differential, Continuous DCR Current Sensing
• I
• User Selectable I
• User Selectable Adaptive Dead Time Scheme
• Variable Gate Drive Bias: 5V to 12V
• Multi-Processor Compatible
• Microprocessor Voltage Identification Inputs
• Maximum Allowable Output Voltage of 1.6V
• Overcurrent Protection
• Multi-Tiered Overvoltage Protection
• Digital Soft-Start
• Selectable Operation Frequency up to 1.5MHz Per Phase
• Pb-Free (RoHS Compliant)
- 2-Phase or 1-Phase Operation with Internal Drivers
Current Loads
- Differential Remote Voltage Sensing
- ±0.5% System Accuracy Over-Temperature
- Adjustable Reference-Voltage Offset
- Active Pulse Positioning (APP) Modulation
- Adaptive Phase Alignment (APA)
- Precision Channel-Current Balancing
- Phase Dropping
- Voltage Margining Offset
- Switching Frequency Adjustment
- Overvoltage Protection Level Adjustment
- Selects Adaptive Dead Time Scheme
1000_110x or 1000_111x
- PHASE Detect or LGATE Detect for Application
- Intel VR10 and VR11 Modes of Operation
- AMD Mode of Operation
- 8-bit DAC
- Selectable between Intel’s Extended VR10, VR11, AMD
- Dynamic VID Technology
2
C Interface
Flexibility
5-bit, and AMD 6-bit DAC Tables
All other trademarks mentioned are the property of their respective owners.
May 22, 2008
|
Intersil (and design) is a registered trademark of Intersil Americas Inc.
2
Copyright Intersil Americas Inc. 2008. All Rights Reserved
C “Slave Only” Device Address:
ISL6322G
FN6715.0

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isl6322g Summary of contents

Page 1

... This controller also allows the user the flexibility to choose between PHASE detect or LGATE detect adaptive dead time schemes. This ability allows the ISL6322G to be used in a multitude of applications where either scheme is required. Protection features of this controller IC include a set of sophisticated overvoltage, undervoltage, and overcurrent protection ...

Page 2

... Ordering Information PART NUMBER (Note) PART MARKING ISL6322GCRZ* ISL6322G CRZ ISL6322GIRZ* ISL6322G IRZ *Add “-T” suffix for tape and reel. Please refer to TB347 for details on reel specifications. NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations) ...

Page 3

... SDA MODE/DAC VRSEL SELECT VID7 VID6 VID5 DYNAMIC VID4 VID D/A VID3 VID2 VID1 VID0 REF FB COMP OFFSET OFS GND 3 ISL6322G ISL6322G PGOOD SOFT-START AND FAULT LOGIC 0.2V LOAD APPLY TRANSIENT ENHANCEMENT CLOCK AND MODULATOR WAVEFORM GENERATOR ∑ ∑ E/A CHANNEL I CURRENT AVG 1 BALANCE N ...

Page 4

... SHOOT- GATE CONTROL THROUGH LOGIC PROTECTION SDA BUS MASTER SCL SDA SCL SLAVE ADDRESS: 1000_110x NOTE: PIN A0 SELECTS THE SLAVE ADDRESS FOR THE ISL6322G PVCC BOOT UGATE 20kΩ PHASE 10kΩ LGATE +5V +5V SDA SCL SDA ISL6322G ISL6322G A0 SLAVE ADDRESS: ...

Page 5

... Typical Application - ISL6322G FB VDIFF COMP VSEN RGND +5V VCC OFS IOUT FS REF SCL ISL6322G SDA SS/RST/A0 VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 VRSEL PGOOD EN_PH2 +12V EN GND 5 ISL6322G ISL6322G +12V BOOT1 UGATE1 PHASE1 LGATE1 ISEN1- ISEN1+ +12V PVCC BOOT2 UGATE2 ...

Page 6

... BOOT - PHASE - 0. 0.3V BOOT Recommended Operating Conditions + 0.3V BOOT VCC Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+5V ±5% PVCC Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . +5V to 12V ±5% Ambient Temperature ISL6322GCRZ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C ISL6322GIRZ . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C TEST CONDITIONS high VCC high PVCC VCC rising VCC falling ...

Page 7

... Overcurrent Trip Level - Individual Channel PROTECTION Undervoltage Threshold Undervoltage Hysteresis Overvoltage Threshold During Soft-Start Overvoltage Threshold (Default) Overvoltage Threshold (Alternate) Overvoltage Hysteresis 7 ISL6322G ISL6322G TEST CONDITIONS R = 10kΩ from OFS to GND OFS R = 30kΩ from OFS to VCC OFS R = 10k to ground, (Note 3) ...

Page 8

... Lower Drive Source Resistance Lower Drive Sink Resistance OVER TEMPERATURE SHUTDOWN (Note 3) Thermal Shutdown Setpoint Thermal Recovery Setpoint Timing Diagram t PDHUGATE UGATE LGATE t FLGATE 8 ISL6322G ISL6322G TEST CONDITIONS 12V, 3nF load, 10% to 90% RUGATE; PVCC 12V, 3nF load, 10% to 90% RLGATE; PVCC 12V, 3nF load, 90% to 10% FUGATE ...

Page 9

... VDIFF is the output of the differential remote-sense amplifier. The voltage on this pin is equal to the difference between VSEN and RGND. 9 ISL6322G ISL6322G FB and COMP These pins are the internal error amplifier inverting input and output respectively. FB, VDIFF, and COMP are tied together through external R-C networks to compensate the regulator. ...

Page 10

... The ISL6322G controller helps simplify implementation by integrating vital functions and requiring minimal external components. The “Block Diagram” on page 3 provides a top level view of 2 multiphase power conversion using the ISL6322G controller. C interface registers. FIGURE 1. PWM AND INDUCTOR-CURRENT WAVEFORMS ...

Page 11

... PWM time interval. This prevents the occurrence of double PWM pulses occurring during a single period. To further improve the transient response, ISL6322G also implements Intersil’s proprietary Adaptive Phase Alignment (APA) technique, which turns on all phases together under transient events with large step current ...

Page 12

... Phase Dropping The ISL6322G has the ability to change the number of active phases firing on-the-fly. This can be done through one of two ways; through the use of the EN_PH2 pin, and through the interface. The EN_PH2 pin is a digital logic input pin. Tieing this pin high commands the part to operate in single phase mode only ...

Page 13

... OPTIONAL 2 Output Voltage Setting The ISL6322G uses a digital to analog converter (DAC) to generate a reference voltage based on the logic signals at the VID pins. The DAC decodes the logic signals into one of the discrete voltages shown in Tables and 5. In Intel modes of operation, each VID pin is pulled internal 1.2V voltage by a weak current source (40µ ...

Page 14

... ISL6322G TABLE 2. VR10 (EXTENDED) VOLTAGE IDENTIFICATION VID6 VDAC VID4 0 1 1.58750 1.58125 1.57500 1.56875 1.56250 1.55625 1.55000 ...

Page 15

... ISL6322G TABLE 2. VR10 (EXTENDED) VOLTAGE IDENTIFICATION VID6 VDAC VID4 1 1 1.10000 1.09375 OFF OFF OFF OFF 1.08750 ...

Page 16

... ISL6322G TABLE 3. VR11 VOLTAGE IDENTIFICATION VDAC VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 1 1 1.44375 1.43750 1.43125 1.42500 1.41875 ...

Page 17

... ISL6322G TABLE 3. VR11 VOLTAGE IDENTIFICATION VDAC VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 0 1 0.95625 0.95000 0.94375 0.93750 0.93125 ...

Page 18

... TABLE 5. AMD 6-BIT VOLTAGE IDENTIFICATION CODES VID5 VID4 VID3 VID2 VID1 ISL6322G TABLE 5. AMD 6-BIT VOLTAGE IDENTIFICATION VID5 VID4 VID0 VDAC 0 1 Off 0 0 0.800 0 1 0.825 0 0 0.850 0 1 0.875 0 0 0.900 0 1 0.925 ...

Page 19

... FIGURE 6. OUTPUT VOLTAGE AND LOAD-LINE 1 0.3750 Output-Voltage Offset Programming The ISL6322G allows the designer to accurately adjust the offset voltage by connecting a resistor, R pin to VCC or GND. When R and VCC, the voltage across it is regulated to 1.6V. This causes a proportional current ( OFS regulated to 0.4V, and I ...

Page 20

... ISL6322G responds differently to a dynamic VID change than E/A when in Intel VR10 or VR11 mode. In the AMD modes, the ISL6322G still checks the VID inputs on the positive edge of REF an internal 3MHz clock. In these modes the VID code can be changed by more than a 1-bit step at a time new code is established and it remains stable for 3 consecutive readings (1µ ...

Page 21

... FIGURE 9. BOOTSTRAP CAPACITANCE vs BOOT RIPPLE Gate Drive Voltage Versatility The ISL6322G provides the user flexibility in choosing the gate drive voltage for efficiency optimization. The controller ties the upper and lower drive rails together. Simply applying a voltage from 12V on PVCC sets both gate drive rail voltages simultaneously ...

Page 22

... VBOOT voltage. Then, the controller will regulate the VR voltage at 1.1V for another fixed period t ISL6322G will read the VID signals. If the VID code is valid, ISL6322G will initiate the second soft-start ramp until the output voltage reaches the VID voltage plus/minus any offset voltage ...

Page 23

... FIGURE 13. SOFT-START WAVEFORMS FOR . The typical value D5 Pre-Biased Soft-Start The ISL6322G also has the ability to start up into a pre-charged output, without causing any unnecessary disturbance. The FB pin is monitored during soft-start, and should it be higher than the equivalent internal ramping reference voltage, the output drives hold both MOSFETs off. ...

Page 24

... OVP protection circuitry is disabled from the beginning of the dynamic VID transition, until 50µs after the internal DAC reaches the final VID setting. This is the only time during operation of the ISL6322G that the OVP circuitry is not active. Pre-POR Overvoltage Protection ...

Page 25

... FIGURE 15. OVERCURRENT BEHAVIOR IN HICCUP MODE Individual Channel Overcurrent Limiting The ISL6322G has the ability to limit the current in each individual channel without shutting down the entire regulator. – 6 ⋅ ⋅ ⋅ ⎛ ...

Page 26

... The level of logic “0” and logic “1” is dependent on associated value Specifications” table on page 6. One clock pulse is generated for each data bit transferred. The ISL6322G is a “SLAVE only” device, so the SCL line must always be controlled by an external master. 2 ...

Page 27

... ISL6322G can be written individually with two separate write transactions or sequentially with one write transaction by sending two data bytes as described below. To write to a single register in the ISL6322G, the master ACKNOWLEDGE sends a control byte with the R/W bit set to 0, indicating a FROM SLAVE write ...

Page 28

... Stop condition, the master follows with a new Start condition, and then sends a new control byte with the R/W bit set to 1, indicating a read. The ISL6322G will then respond by sending the master an Acknowledge, followed by the data byte stored in that register. The master must then send a Not Acknowledge followed by a Stop command, which will complete the read transaction ...

Page 29

... ISL6322G TABLE 8. REGISTER RGS1 (VOLTAGE MARGINING BIT1 BIT0 BIT7 BIT6 V OFFSET VO1 VO0 (mV 125 137 150 162 175 187 ...

Page 30

... ISL6322G BIT1 BIT0 NUMBER OF ADAPTIVE DEADTIME FS1 FS0 CHANNELS CONTROL 0 0 2-Phase PHASE DETECT 0 1 2-Phase PHASE DETECT 1 0 2-Phase PHASE DETECT 1 1 2-Phase PHASE DETECT 0 0 2-Phase ...

Page 31

... – + ------------------------------------- - ----- - , ( ) LOW ⎝ ⎠ ISL6322G BIT1 BIT0 NUMBER OF ADAPTIVE DEADTIME FS1 FS0 CHANNELS 1-Phase LGATE DETECT 1-Phase LGATE DETECT An additional term can be added to the lower-MOSFET loss equation to account for additional loss accrued during the dead time when inductor current is flowing through the lower-MOSFET body diode ...

Page 32

... QFN package is approximately 3.5W at room temperature. See “Layout Considerations” on page 36 for thermal transfer improvement suggestions. When designing the ISL6322G into an application recommended that the following calculation is used to ensure safe operation at the desired frequency for the selected MOSFETs. The total gate drive power losses, P the gate charge of MOSFETs and the integrated driver’ ...

Page 33

... The total power dissipation in the controller itself, P can be roughly estimated with Equation 29. Inductor DCR Current Sensing Component Selection The ISL6322G senses each individual channel’s inductor current by detecting the voltage across the output inductor DCR of that channel (as described in “Continuous Current Sampling” on page 12). As Figure 21 illustrates, an R-C ...

Page 34

... Capacitors are characterized according to their capacitance, ESR, and ESL (equivalent series inductance). ISL6322G At the beginning of the load transient, the output capacitors supply all of the transient current. The output voltage will initially deviate by an amount approximated by the voltage drop across the ESL ...

Page 35

... S – ISL6322G 1000 (EQ. 38) 100 10 Input Capacitor Selection The input capacitors are responsible for sourcing the AC component of the input current flowing into the upper MOSFETs. Their RMS current capacity must be sufficient to handle the ac component of the current drawn by the upper MOSFETs which is related to duty cycle and the number of active phases ...

Page 36

... VCC and PVCC, and many of the components surrounding the controller including the feedback network and current sense components. Locate the VCC/PVCC bypass capacitors as close to the ISL6322G as possible especially important to locate the components associated with the feedback circuit close to their respective controller pins, since they belong to a high-impedance circuit loop, sensitive to EMI pick-up ...

Page 37

... Thermal Management For maximum thermal performance in high current, high switching frequency applications, connecting the thermal GND pad of the ISL6322G to the ground plane with multiple vias is recommended. This heat spreading allows the part to achieve its full thermal potential also recommended that the controller be placed in a direct path of airflow if possible to help thermally manage the part ...

Page 38

... However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 38 ISL6322G LOCATE CLOSE TO IC (MINIMIZE CONNECTION PATH) +12V ...

Page 39

... L48.7x7 48 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 4, 10/06 7.00 6 PIN 1 INDEX AREA (4X) 0.15 TOP VIEW ( TYP ) ( TYPICAL RECOMMENDED LAND PATTERN 39 ISL6322G 4X 5.5 A 44X 0. 48X 0 . 40± BOTTOM VIEW ± SIDE VIEW ( 44X REF C ( 48X 0 ...

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