ISL6424 Intersil, ISL6424 Datasheet

ISL6424

Manufacturer Part Number

ISL6424

Description

Single Output LNB Supply and Control Voltage Regulator

Manufacturer

Intersil

Datasheet

1.ISL6424.pdf (12 pages)

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Dual Output LNB Supply and Control

Voltage Regulator with I

Advanced Satellite Set-Top Box Designs

The ISL6424 is a highly integrated voltage regulator and

interface IC, specifically designed for supplying power and

control signals from advanced satellite set-top box (STB)

modules to the low noise blocks (LNBs) of two antenna

ports. The device is comprised of two independent current-

mode boost PWMs and two low-noise linear regulators along

with the circuitry required for 22kHz tone generation,

modulation and I

total LNB supply design simple, efficient and compact with

low external component count.

Two independent current-mode boost converters provide the

linear regulators with input voltages that are set to the final

output voltages, plus typically 1.2V to insure minimum power

dissipation across each linear regulator. This maintains

constant voltage drops across each linear pass element

while permitting adequate voltage range for tone injection.

The final regulated output voltages are available at two

output terminals to support simultaneous operation of two

antenna ports for dual tuners. The outputs for each PWM are

set to 13V or 18V by independent voltage select commands

(VSEL1, VSEL2) through the I

compensate for the voltage drop in the coaxial cable, the

selected voltage may be increased by 1V with the line length

compensation (LLC) feature. All the functions on this IC are

controlled via the I

and two bits will report the diagnostic status. Separate enable

commands sent on the I

mode control for each PWM and linear combination, disabling

the output into shutdown mode.

Each output channel is capable of providing 750mA of

continuous current. The overcurrent limit can be digitally

programmed. The SEL18V pin allows the 13V to 18V

transition with an external pin, overriding the I

The ISL6424 is offered in a 32 Ld 5x5 QFN.

C device interface. The device makes the

C bus by writing 8 bits on System

C bus provide independent standby

C bus. Additionally, to

C Interface for

Data Sheet

C input.

1-888-INTERSIL or 1-888-468-3774

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

Features

• Single Chip Power Solution

• Switch-Mode Power Converter for Lowest Dissipation

• I

• External Pins to Select 13V/18V Option

• DSQIN1&2 and SEL18V1&2 pins 2.5V Logic Compatible

• Built-In Tone Oscillator Factory Trimmed to 22kHz

• Internal Over-Temperature Protection and Diagnostics

• Internal Overload and Overtemp Flags (Visible on I

• LNB Short-Circuit Protection and Diagnostics

• QFN Package

• Pb-Free Plus Anneal Available (RoHS Compliant)

Applications

• LNB Power Supply and Control for Satellite Set-Top Box

References

• Tech Brief 389 (TB389) - “PCB Land Pattern Design and

Ordering Information

*Add “-T” suffix for tape and reel.

NOTE: Intersil Pb-free plus anneal products employ special Pb-free

material sets; molding compounds/die attach materials and 100%

matte tin plate termination finish, which are RoHS compliant and

compatible with both SnPb and Pb-free soldering operations. Intersil

Pb-free products are MSL classified at Pb-free peak reflow

temperatures that meet or exceed the Pb-free requirements of

IPC/JEDEC J STD-020.

ISL6424ER

ISL6424ERZ (Note) ISL6424ERZ -20 to 85 32 Ld 5x5 QFN

September 13, 2005

- True Dual Operation for 2-Tuner/2-Dish Applications

- Both Outputs May be Enabled Simultaneously at

- Integrated DC-DC Converter and I

- Boost PWMs with > 92% Efficiency

- Selectable 13V or 18V Outputs

- Digital Cable Length Compensation (1V)

- Registered Slave Address 0001 00XX

- Full 3.3V/5V Operation up to 400kHz

- Facilitates DiSEqC (EUTELSAT) Encoding

- Compliant to JEDEC PUB95 MO-220 QFN - Quad Flat

- Near Chip-Scale Package Footprint

Surface Mount Guidelines for QFN Packages”; Available

on the Intersil website, www.intersil.com

C Compatible Interface for Remote Device Control

Maximum Power

No Leads - Product Outline

PART # *

All other trademarks mentioned are the property of their respective owners.

Intersil (and design) is a registered trademark of Intersil Americas Inc.

ISL6424ER -20 to 85 32 Ld 5x5 QFN L32.5x5

MARKING

PART

TEMP.

(°C)

www.DataSheet4U.com

C Interface

(Pb-free)

PACKAGE

ISL6424

FN9175.3

L32.5x5

DWG. #

PKG.

Related parts for ISL6424

ISL6424 Summary of contents

Page 1

... C input. PART # * ISL6424ER ISL6424ERZ (Note) ISL6424ERZ - 5x5 QFN *Add “-T” suffix for tape and reel. NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations ...

Page 2

... Pinout ISL6424 (QFN) TOP VIEW PGND2 1 CS2 2 SGND 3 SEL18V1 4 ISL6424ER SEL18V2 5 BYP 6 PGND1 7 GATE1 ISL6424 26 25 CPSWOUT 24 TCAP2 23 DSQIN2 22 VO2 21 20 AGND 19 VO1 DSQIN1 18 TCAP1 www.DataSheet4U.com FN9175.3 September 13, 2005 ...

Page 3

Block Diagram OLF1 OVERCURRENT COUNTER PROTECTION DCL LOGIC SCHEME 1 PWM OC1 LOGIC GATE1 8 Q CLK1 S PGND1 7 ILIM1 CS - AMP CS1 ∑ 9 SLOPE COMPENSATION COMP1 11 - FB1 10 VREF1 VSW1 12 VO1 19 ON ...

Page 4

... D FDS6612A R2 0.10 R9 C24 8 100 GATE1 GATE2 9 CS1 CS2 100pF 7 E PGND PGND2 11 U1 COMP1 COMP2 ISL6424 FB1 FB2 12 VSW1 VSW2 19 68K 1500pF VO1 VO2 18 DSQIN1 DSQIN2 33 EP C30 0.01µ 100 R8 SW1 100 12 DISQ1 ...

Page 5

... Line Regulation Load Regulation Dynamic Output Current Limiting Dynamic Overload Protection Off Time Dynamic Overload Protection On Time 5 ISL6424 Thermal Information Thermal Resistance (Typical, Notes 1, 2) QFN Package Maximum Junction Temperature (Note 150°C Maximum Storage Temperature Range . . . . . . . . . . . -40°C to 150°C Maximum Lead Temperature (Soldering 10s 300°C Operating Temperature Range . . . . . . . . . . . . . . . . . . -20° ...

Page 6

... VO1 for LNB1, VO2 for LNB2. Voltage programming signals VSEL1, VSEL2, LLC1, and LLC2 are implemented via the I IO1 = IO2 = 350mA/750mA. 6. Guaranteed by design. 7. Unused DSQIN 1&2 pins should be connected to GND. SEL18V1&2 pins have 200K internal pulldown resistors. 6 ISL6424 = -20°C to +85°C, unless otherwise noted. Typical values are access to the system. (Continued) ...

Page 7

... TEMPERATURE (°C) FIGURE 1. OUTPUT CURRENT DERATING Functional Description The ISL6424 dual output voltage regulator makes an ideal choice for advanced satellite set-top box and personal video recorder applications. Both supply and control voltage outputs for two low-noise blocks (LNBs) are available simultaneously in any output configuration. The device ...

Page 8

... SCL are bidirectional lines, connected to a positive supply voltage via a pull up resistor. (Pull up resistors to positive supply voltage must be externally connected). When the bus is free the end both lines are HIGH. The output stages of ISL6424 will have an open drain/open collector in order to perform the wired-AND + t ON OFF function ...

Page 9

... SDA line remains at the HIGH level during the ninth clock pulse time. In this case, the master transmitter can generate the STOP information in order to abort the transfer. The ISL6424 will not generate the acknowledge if the POWER OK signal from the UVLO is LOW. SCL ...

Page 10

... Transmitted Data ( bus WRITE mode When the R/W bit in the chip is set to 0, the main microprocessor can write on the system registers (SR1/SR2 the ISL6424 via I C bus. These will be written by the TABLE 5. SYSTEM REGISTER (SR1 AND SR2) CONFIGURATION SR DCL ISEL1 ENT1 ...

Page 11

... Received Data ( bus READ MODE The ISL6424 can provide to the master a copy of the system 2 register information via the I C bus in read mode. The read mode is Master activated by sending the chip address with R/W bit set the following Master generated clock bits, the ISL6424 issues a byte on the SDA data bus line (MSB transmitted first) ...

Page 12

... However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 12 ISL6424 L32.5x5 32 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE (COMPLIANT TO JEDEC MO-220VHHD-2 ISSUE C ...

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