ISL6504 Intersil Corporation, ISL6504 Datasheet
ISL6504
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ISL6504 Summary of contents
Page 1
... The IC integrates three linear controllers/regulators, switching, monitoring and control functions into a 16-pin wide-body SOIC or 20-pin QFN 6x6 package. The ISL6504, ISL6504A operating mode (active outputs or sleep outputs) is selectable through two digital control pins, S3 and S5. ...
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Block Diagram 3V3DLSB EA3 + - TO UV DETECTOR 1V5SB FAULT UV DETECTOR UV COMP - 4.10V 5VDL GND 3V3DL 3V3 EA4 - + 4.4V/3.4V 3V3 MONITOR 2.75V/2.60V MONITOR AND CONTROL + 10mA 1.265V - + + - SS S3 ...
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... SX 2 Typical Application +5VIN +12VIN +5VSB +3.3VIN VOUT1 1.5VSB COUT1 Q1 Q2 VOUT3 3.3VDUAL/3.3VSB COUT3 FAULT SLP_S3 SLP_S5 SHUTDOWN 3 ISL6504, ISL6504A LINEAR LINEAR REGULATOR REGULATOR LINEAR CONTROLLER CONTROL ISL6504/A LOGIC FIGURE 2. 5VSB 3V3 1V5SB 1V2VID RDLA VID_CT 3V3DLSB VID_PG 3V3DL ISL6504/A ...
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... OUT2 Regulation 1V2VID Nominal Voltage Level 1V2VID Undervoltage Rising Threshold 1V2VID Undervoltage Hysteresis 1V2VID Output Current 4 ISL6504, ISL6504A Thermal Information Thermal Resistance (Typical) SOIC Package (Note QFN Package (Note Maximum Junction Temperature (Plastic Package .150 Maximum Storage Temperature Range . . . . . . . . . -65 Maximum Lead Temperature (Soldering 10s .300 (SOIC - Lead Tips Only) For Recommended soldering conditions see Tech Brief TB389 ...
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... CONTROL I/O (S3, S5, FAULT) High Level Input Threshold Low Level Input Threshold S3, S5 Internal Pull-up Impedance to 5VSB FAULT Output Impedance TEMPERATURE MONITOR Fault-Level Threshold (Note 4) Shutdown-Level Threshold (Note 4) NOTES: 3. Guaranteed by Correlation. 4. Guaranteed by Design. 5 ISL6504, ISL6504A SYMBOL TEST CONDITIONS ) OUT3 V 3V3DL 3V3DLSB 5VSB ...
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... MOS transistor. This pin is also monitored for undervoltage events. 5VDLSB (Pin 11) Connect this pin to the gate of a suitable P-MOSFET or bipolar PNP. ISL6504 sleep state, this transistor is switched on, connecting the ATX 5V 5V DUAL state, this transistor is switched on, connecting the ATX ...
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... Additionally, the S3 pin features a 200µs delay in transitioning to sleep states. Once the S3 pin goes low, an internal timer is activated. At the end of the 200µs interval, if the S5 pin is low, the ISL6504/A switches into S5 sleep state; if the S5 pin is high, the ISL6504/A goes into S3 sleep state. ...
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... SS (soft-start) pin voltage. As the SS pin voltage slews from about 1.25V to 2.5V, the input clamp allows a rapid and controlled output voltage rise. Figures 7 (ISL6504) and 8 (ISL6504A) show the soft-start sequence for the typical application start-up into a sleep state. At time T0 5V (bias) is applied to the circuit. At time ...
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... DUAL as it heats up again, it will repeat the FAULT cycle). In ISL6504/A applications, loss of the active ATX output (3.3V IN active state operation causes the chip to switch to S5 sleep state, in addition to reporting the input UV condition on the FAULT pin ...
Page 10
... The built-in soft-start circuitry allows tight control of the slew- up speed of the output voltages controlled by the ISL6504, thus enabling power-ups free of supply drop-off events. Since the outputs are ramped linear fashion, the ...
Page 11
... If the ATX supply does not meet the specifications, certain imbalances between the ATX’s outputs and the ISL6504/A’s regulation levels could have as a result a brisk transfer of energy from the input capacitors to the supplied outputs. At the transition between active and ...
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... C4 U1 330mF ISL6504/A FAULT 9 1V5SB GND 0.1mF FIGURE 12. TYPICAL ISL6504/A APPLICATION DIAGRAM output during sleep states, DUAL , however, has to be DS(ON) DUAL voltage, the 1.2V SB DUAL SB C1 1mF VID_PG ‘VID PGOOD’ 14 VID_CT 15 C2 0.1mF R2 10k +1.2VVID 1V2VID ...
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... The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. 13 ISL6504, ISL6504A M16.3 (JEDEC MS-013-AA ISSUE C) 16 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE M B ...
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... Quad Flat No-Lead Plastic Package (QFN) Micro Lead Frame Plastic Package (MLFP) 14 ISL6504, ISL6504A L20.6x6 20 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE (COMPLIANT TO JEDEC MO-220VJJB ISSUE C) SYMBOL MIN 0. θ - NOTES: 1. Dimensioning and tolerancing conform to ASME Y14.5-1994. ...
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... However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 15 ISL6504, ISL6504A M16.15 (JEDEC MS-012-AC ISSUE C) 16 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE ...