ISL6556A Intersil Corporation, ISL6556A Datasheet
ISL6556A
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ISL6556A Summary of contents
Page 1
... ISL6556A with Intersil MOSFET driver IC. Dynamic-VID™ technology allows seamless on-the-fly VID changes. The offset pin allows accurate voltage offset settings that are independent of VID setting. The ISL6556A uses 5V bias and has a built-in shunt regulator to allow 12V bias using only a small external limiting resistor. ...
Page 2
... VDIFF PGOOD RGND x1 VSEN OVP +200mV OFS OFFSET REF DAC VID4 VID3 DYNAMIC VID2 VID VID1 D/A VID0 VID12.5 COMP FB 2 ISL6556A OVP VCC OVP R S POWER-ON LATCH RESET (POR) Q SOFT START CLOCK AND AND SAWTOOTH FAULT LOGIC GENERATOR E/A CHANNEL CURRENT BALANCE I_TRIP OC ...
Page 3
... RGND x1 VSEN OVP +200mV OFS OFFSET OFSOUT REF DAC VID4 VID3 DYNAMIC VID2 VID VID1 D/A VID0 VID12.5 COMP FB 3 ISL6556A OVP VCC OVP R S POWER-ON LATCH RESET (POR) Q SOFT START CLOCK AND AND SAWTOOTH FAULT LOGIC GENERATOR + E/A - CHANNEL CURRENT BALANCE I_TRIP ...
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... Typical Application of ISL6556ACB +5V FB COMP VCC DAC VDIFF VSEN REF RGND PGOOD OVP ISEN1 ISL6556ACB VID4 PWM1 VID3 PWM2 VID2 ISEN2 VID1 PWM3 VID0 ISEN3 VID12.5 PWM4 OFS FS ISEN4 GND VID_PGOOD (BUFFERED) 4 ISL6556A +12V VCC BOOT UGATE PVCC PHASE HIP6601B ...
Page 5
... Typical Application of ISL6556ACR +5V FB COMP VCC EN VDIFF DAC VSEN RGND REF PGOOD OVP OFSOUT ISL6556ACR VID4 ISEN1 VID3 PWM1 VID2 PWM2 ISEN2 VID1 PWM3 VID0 ISEN3 VID12.5 PWM4 OFS FS ISEN4 ENLL EN GND R T VID_PGOOD 5 ISL6556A +12V VCC BOOT UGATE PVCC PHASE ...
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... VCC tied to 12VDC through 300 resistor, R VCC tied to 12VDC through 300 resistor, R VCC Rising VCC Falling EN Rising Hysteresis Fault Reset ENLL=5V (Note 4) (Note 4) (Note 4) VID = 010100 (ISL6556ACR Only) Offset resistor connected to ground Voltage below VCC, offset resistor connected to VCC 105 C ...
Page 7
... Connecting the 12V supply to EN through an appropriate resistor divider provides a means to synchronize power-up of the controller and the MOSFET driver ICs. When EN is driven above 1.24V, the ISL6556A is active depending on status of ENLL, the internal POR, and pending fault states. Driving EN below 1.14V will clear all fault states and prime the ISL6556 to soft start when re-enabled ...
Page 8
... This pin is implemented in QFN ISL6556A only. It’s a logic- level enable input for the controller. When asserted to a logic high, the ISL6556A is active depending on status of EN, the internal POR, VID inputs and pending fault states. Deasserting ENLL will clear all fault states and prime the ISL6556A to soft start when re-enabled ...
Page 9
... The ISL6556A controller helps simplifying the implementation by integrating vital functions and requiring minimal output components. The block diagrams on pages 2 and 3 provide top level views of multi-phase power conversion using the ISL65556ACB and ISL6556ACR controllers ...
Page 10
... PWM Operation The timing of each converter leg is set by the number of active channels. The default channel setting for the ISL6556A is four. One switching cycle is defined as the time between PWM1 pulse termination signals. The pulse termination signal is the internally generated clock signal that triggers the falling edge of PWM1. The cycle time of the ...
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... OUT the DAC) and offset errors in the OFS current source, remote-sense and error amplifiers. Intersil specifies the guaranteed tolerance of the ISL6556A to include the combined tolerances of each of these elements. PWM1 The output of the error amplifier, V sawtooth waveform to generate the PWM signals. The PWM ...
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... ISL6556A TABLE 1. VOLTAGE IDENTIFICATION (VID) CODES (Continued) VID4 VID12.5 VDAC 1 0 0.8375V 1 1 0.8500V 1 0 0.8625V 1 1 0.8750V 1 0 0.8875V 1 1 0.9000V 1 0 ...
Page 13
... R DROOP ISEN Output-Voltage Offset Programming The ISL6556A allows the designer to accurately adjust the offset voltage. When a resistor connected between OFS OFS and VCC, the voltage across it is regulated to 2.0V. This causes a proportional current (I OFS R is connected to ground, the voltage across it is OFS regulated to 0 ...
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... The schematic in Figure 8 demonstrates sequencing the ISL6556A with the HIP660X family of Intersil MOSFET drivers, which require (EQ. 9) 12V bias. 3. (ISL6556ACR only) The voltage on ENLL must be logic high to enable the controller. This pin is typically is 22nF based connected to the VID_PGOOD. The ISL6556ACB has REF this signal internally connected high ...
Page 15
... FIGURE 9. SOFT-START WAVEFORMS WITH AN UN-BIASED OUTPUT. FSW = 500kHz Fault Monitoring and Protection The ISL6556A actively monitors output voltage and current to detect fault conditions. Fault monitors trigger protective measures to prevent damage to a microprocessor load. One common power good indicator is provided for linking to external system monitors ...
Page 16
... The Intersil drivers respond to the high-impedance input by turning off both upper and lower MOSFETs. If the over-voltage condition reoccurs, the ISL6556A will again command the lower MOSFETs to turn on. The ISL6556A will continue to protect the load in this fashion as long as the over-voltage condition recurs. ...
Page 17
... Once the lower MOSFET begins conducting, the current in the upper MOSFET falls to zero as the current in the lower MOSFET 17 ISL6556A ramps up to assume the full inductor current. In Equation 13, the required time for this commutation is t approximated associated power loss is P ...
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... V the peak-to-peak sawtooth signal amplitude as described in Figure 4 and Electrical Specifications. C (OPTIONAL COMP FB + IOUT DROOP - VDIFF LOAD-LINE REGULATED ISL6556A CIRCUIT , has already been chosen The target 0 1 ------------------- > ...
Page 19
... C is the total output capacitance, and N is the number of active channels. Input Supply Voltage Selection The VCC input of the ISL6556A can be connected either directly to a +5V supply or through a current limiting resistor to a +12V supply. An integrated 5.8V shunt regulator maintains the voltage on the VCC pin when a +12V supply is used. A 300 resistor is suggested for limiting the current into the VCC pin to a worst-case maximum of approximately 25mA ...
Page 20
... The result from the high current slew rates produced by the upper MOSFETs turn on and off. Select low ESL ceramic capacitors and place one as close as possible to each upper MOSFET drain to minimize board parasitic impedances and maximize suppression. 20 ISL6556A 0.3 0.2 0 ...
Page 21
... The ISL6556A can be placed off to one side or centered relative to the individual phase switching components. Routing of sense lines and PWM signals will guide final placement. Critical small signal components to place close to the controller include the ISEN resistors ...
Page 22
... The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. Controlling dimension: MILLIMETER. Converted inch dimen- sions are not necessarily exact. 22 ISL6556A M28.3 (JEDEC MS-013-AE ISSUE C) 28 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE M B ...
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... However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 23 ISL6556A L32.5x5B 32 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE (COMPLIANT TO JEDEC MO-220VHHD-2 ISSUE C ...