ISL70001SRH Intersil Corporation, ISL70001SRH Datasheet
ISL70001SRH
Related parts for ISL70001SRH
ISL70001SRH Summary of contents
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... J The ISL70001SRH utilizes peak current-mode control with integrated compensation and switches at a fixed frequency of 1MHz. Two ISL70001SRH devices can be synchronized 180° out-of-phase to reduce input RMS ripple current. These attributes reduce the number and size of external components required, while providing excellent output transient response ...
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... These Intersil Pb-free Hermetic packaged products employ 100% Au plate - e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. 2. For Moisture Sensitivity Level (MSL), please see device information page for ISL70001SRH. For more information on MSL please see techbrief TB363. ...
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... IC. This pin is the synchronization I/O for the IC. When configured as an output (Master Mode), this pin drives the SYNC input of another ISL70001SRH. When configured as an input (Slave Mode), this pin accepts the SYNC output from another ISL70001SRH or an external clock. Synchronization of the slave unit is 180° out-of-phase with respect to the master unit. If synchronizing to an external clock, the clock must be SEE hardened and the frequency must be within the range of 1MHz ± ...
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... EN 23 PORSEL 4 ISL70001SRH (Continued) This pin is the power-good output. This pin is an open drain logic output that is pulled to DGND when the output voltage is outside a ±11% typical regulation window. This pin can be pulled up to any voltage from 0V to 5.5V, independent of the supply voltage. A nominal 1kΩ to 10kΩ ...
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... VSENSE 10nF PORSEL www.DataSheet4U.com FIGURE 1. 5V INPUT SUPPLY VOLTAGE WITH MASTER MODE SYNCHRONIZATION 5 ISL70001SRH PVIN1 PVIN2 PVIN3 PVIN4 PVIN5 PVIN6 DVDD 1µF ISL70001SRH DGND AVDD AGND EN M/S TDI TDO ZAP LX1 LX2 LX3 LX4 LX5 1µH LX6 470µF 20V 1kΩ ...
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... VSENSE 10nF PORSEL www.DataSheet4U.com FIGURE 2. 3.3V INPUT SUPPLY VOLTAGE WITH SLAVE MODE SYNCHRONIZATION 6 ISL70001SRH (Continued) PVIN1 PVIN2 PVIN3 PVIN4 PVIN5 PVIN6 DVDD 1µF ISL70001SRH DGND AVDD 1µF AGND EN M/S TDI TDO ZAP LX1 LX2 LX3 LX4 LX5 1µH LX6 470µF 20V 1kΩ ...
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... Upper Device r DS(ON) Lower Device r DS(ON) LXx Output Leakage Deadtime Efficiency 7 ISL70001SRH Unless otherwise noted AVDD = DVDD = PVINx = 5.5V; GND = AGND IN = DGND = PGNDx = TDI = TDO = ZAP = 0V 0.65V; PORSEL = V and GND for V < 4.5V, SYNC = LXx = Open Circuit; PGOOD is pulled resistor; REF is bypassed to GND with a 220nF capacitor bypassed to GND with a 100nF capacitor ...
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... During an output short-circuit, peak current through the power block(s) can continue to build beyond the overcurrent trip level 3A. With all six power blocks connected, peak current through the power blocks and output inductor could reach (6 x 2.5A 18A. The output inductor must support this peak current without saturating. 8 ISL70001SRH Unless otherwise noted AVDD = DVDD = PVINx = 5.5V; GND = AGND IN = DGND = PGNDx = TDI = TDO = ZAP = 0V ...
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... SYNC output of a Master regulator external clock. Operation Initialization The ISL70001SRH initializes based on the state of the power-on reset (POR) monitor of the PVINx inputs and the state of the EN input. Successful initialization prompts a soft-start interval and the regulator begins ...
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... LXx pins are held in a high-impedance state. Enable and Disable After the POR input requirement is met, the ISL70001SRH remains in shutdown until the voltage at the enable input rises above the enable threshold. As shown in Figure 5, the enable circuit features a comparator type input. In addition to simple logic ...
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... The PGOOD pin should be bypassed to DGND with a 10nF ceramic capacitor to mitigate SEE. Fault Monitoring and Protection The ISL70001SRH actively monitors output voltage and current to detect fault conditions. Fault conditions trigger protective measures to prevent damage to the regulator and external load device. ...
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... P-P(MAX) Another consideration in selecting the output capacitors is loop stability. The total output capacitance sets the dominant pole of the PWM. Because the ISL70001SRH uses integrated compensation techniques, it necessary to restrict the output capacitance in order to optimize loop stability. The recommended load capacitance can be estimated using Equation 10 ...
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... RMS ripple current required by the circuit. Ceramic capacitors with X7R dielectric are recommended. Alternately, a combination of low ESR solid tantalum capacitors and ceramic capacitors with X7R dielectric may be used. The ISL70001SRH requires a minimum effective input capacitance of 100µF for stable operation. PCB Design PCB design is critical to high-frequency switching regulator performance ...
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... Silicon ASSEMBLY RELATED INFORMATION Substrate Potential PGND ADDITIONAL INFORMATION Worst Case Current Density < Transistor Count 25030 Layout Characteristics Step and Repeat 5720µm x 5830µm Connect PGND to PGNDx ISL70001SRH PVIN1 LX1 PGND1 PGND2 FB EN PORSEL PVIN6 5 2 A/cm LX2 PVIN2 ...
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... PGND5 LX5 PVIN5 PVIN4 LX4 PGND4 PGND3 LX3 PVIN3 PVIN2 LX2 PGND2 PGND1 LX1 PVIN1 www.DataSheet4U.com SYNC M/S ZAP TDI TDO PGOOD SS DVDD DGND PGND AGND 15 ISL70001SRH TABLE 1. LAYOUT X-Y COORDINATES X µ 478 16 865 17 1295 18 1751 19 2151 20 2838 21 3449 22 4060 23 4845 24 5449 25 5449 ...
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... No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see 16 ISL70001SRH Initial Release. www.intersil.com/products ISL70001SRH http://rel.intersil.com/reports/search.php www.intersil.com/product_tree www.intersil.com/design/quality CHANGE for a complete list of Intersil product families. www.intersil.com/askourstaff www ...