ISL8700 INTERSIL [Intersil Corporation], ISL8700 Datasheet
ISL8700
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ISL8700 Summary of contents
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... Ld SOIC M14. SOIC M14. SOIC M14.15 * SEQ_EN and FAULT are not available on ISL8700 and ISL8701 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 All other trademarks mentioned are the property of their respective owners. ...
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... TOP VIEW ENABLE_D VIN 1 14 ENABLE_C ENABLE_B ENABLE_A TIME GND ISL8700, ISL8701, ISL8702 ISL8701 (14 LD SOIC) TOP VIEW ENABLE#_D VIN 1 14 ENABLE# ENABLE# ENABLE# TIME GND NC ...
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... FAULT Pull-down Current SEQ_EN Pull-up Voltage SEQ_EN Low Threshold Voltage SEQ_EN High Threshold Voltage Delay to ENABLE_A Deasserted 3 ISL8700, ISL8701, ISL8702 Thermal Information Thermal Resistance (Typical, Note SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Maximum Junction Temperature (Plastic Package +125°C +0.3V, to -0.3V Maximum Storage Temperature Range . . . . . . . . . .-65°C to +150°C IN Pb-free Reflow Profile ...
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... ISL8701. Tracks V IN Active high open drain sequenced output. Sequenced on after ENABLE_C and first output to sequence off for the ISL8700, ISL8702. Pulls low with V Active low open drain sequenced output. Sequenced on after ENABLE#_B and sequenced off after ENABLE#_D for the ISL8701. Tracks V IN Active high open drain sequenced output ...
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... TIME capacitor is discharged once V Once ENABLE_A is active (either released high on the ISL8700, ISL8702 or pulled low on the ISL8701), a counter is started and using the resistor timing component, a delay is generated before ENABLE_B is activated. At this time, the counter is restarted using the resistor its timing ...
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... ENABLE_C. Likewise, a delay to ENABLE_B and then ENABLE_A turn-off is determined by TC and TB resistor values respectively. With the ISL8700, ISL8701, a quasi down sequencing of the ENABLE outputs can be achieved by loading the ENABLE pins with various value capacitors to ground. When a simultaneous output latch off is invoked, the caps will set the falling ramp of the various ENABLE outputs thus adjusting the time to Vth for various DC/DC convertors or other circuitry ...
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... RC time constant for an oscillator whose output is fed into a counter generating the timing delay to ENABLE output sequencing. (EQ. 4) The R ⁄ (ISL8700 and ISL8701) to ENABLE_A IN ) the ENABLE_A output (V TIME_VTH IN ⁄ t 770kΩ = VINSEQpd the TIME pin is pulled ...
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... V = 2.5V IN 1.203 1.202 1.201 1.200 V = 24V IN 1.199 1.198 -40 - TEMPERATURE (°C) FIGURE 4. UV/OV RISING THRESHOLD 8 ISL8700, ISL8701, ISL8702 FIGURE 2. ISL8702 OPERATIONAL DIAGRAM t FLTH <t FLTH FIGURE 3. ISL8702 FAULT OPERATIONAL DIAGRAM 310 290 270 250 V = 12V 230 IN 210 190 ...
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... VMON > UV LEVEL FAULT OUTPUT FIGURE 6. VMONITOR RISING TO FAULT 9 ISL8700, ISL8701, ISL8702 bound conditions by being released to pull high to the VHI voltage as shown in Figures 6 and 7. Once the voltage monitoring FAULT is resolved and where applicable, the SEQ_EN(#) is satisfied, sequencing of the ENABLE_X(#) outputs begins. When sequence enabled the ...
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... DELAY = 196ms FIGURE 8. ENABLE_X TO ENABLE_X ENABLING C = 10nF TIME DELAY = 8.5ms FIGURE 10. V /SEQ_EN VALID TO ENABLE_A IN SEQ_EN TIME 0.5V/DIV FIGURE 12. SEQ_EN TO ENABLE_A 10 ISL8700, ISL8701, ISL8702 FIGURE 9. ENABLE_X TO ENABLE_X DISABLING 1V/DIV ENABLE_A FIGURE 13. OV AND UV TRANSIENT IMMUNITY DELAY = 5ms R = 120k TD DELAY = 196ms R ...
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... VIN pin. Coupling from the ENABLE_X pins to the sensitive UV and OV pins can cause false OV/UV events to be detected. This is most relevant for ISL8700, ISL8702 parts due to the ENABLE_A and OV pins being adjacent. This coupling can be reduced by adding a ground trace between UV and the ENABLE/FAULT signals, as shown in Figure 14 ...
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... R7 R Sets Delay from Second to Third ENABLE TC R4, R6, R8, R10, ENABLE_X(#) and FAULT Pull-up Resistors R11 C3 Decoupling Capacitor 12 ISL8700, ISL8701, ISL8702 PULL-UP RESISTORS UV/OV SET RESISTORS Intersil, ISL8702, Quad Undervoltage, Overvoltage Sequencer 1.1kΩ 1%, 0603 88.7kΩ 1%, 0603 9.1kΩ 1%, 0603 0.01µF, 0603 120kΩ 1%, 0603 3.01kΩ ...
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... However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 13 ISL8700, ISL8701, ISL8702 M14.15 (JEDEC MS-012-AB ISSUE C) 14 LEAD NARROW BODY SMALL OUTLINE PLASTIC ...