mk2049-34 Integrated Device Technology, mk2049-34 Datasheet

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mk2049-34

Manufacturer Part Number
mk2049-34
Description
3.3 Volt Communications Clock Vcxo Pll
Manufacturer
Integrated Device Technology
Datasheet

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3.3 VOLT COMMUNICATIONS CLOCK VCXO PLL
Description
The MK2049-34 is a VCXO Phased Locked Loop (PLL)
based clock synthesizer that accepts multiple input
frequencies. With an 8 kHz clock input as a reference, the
MK2049-34 generates T1, E1, T3, E3, ISDN, xDSL, and
other communications frequencies. This allows for the
generation of clocks frequency-locked and phase-locked to
an 8 kHz backplane clock, simplifying clock synchronization
in communications systems. The MK2409-34 can also
accept a T1 or E1 input clock and provide the same output
for loop timing. All outputs are frequency locked together
and to the input.
This part also has a jitter-attenuated Buffer capability. In this
mode, the MK2049-34 is ideal for filtering jitter from 27 MHz
video clocks or other clocks with high jitter.
ICS can customize these devices for many other different
frequencies.
Block Diagram
IDT™ / ICS™ 3.3 VOLT COMMUNICATIONS CLOCK VCXO PLL
F
REQUENCY
I
(T
NPUT
YPICALLY
C
R
LOCK
EFERENCE
S
ELECT
8
K
H
Z
)
4
(M
VCXO-B
G
ASTER
ENERATOR
PLL
C
ASED
LOCK
)
E
(external loop filter)
XTERNAL
M
P
F
REQUENCY
ULTIPLYING
ULLABLE
1
Features
PLL
Packaged in 20-pin SOIC
3.3 V + 5% operation
Fixed I/O phase relationship on all selections
Meets the TR62411, ETS300 011, and GR-1244
specification for MTIE, Pull-in/Hold-in Range, Phase
Transients, and Jitter Generation for Stratum 3, 4, and 4E
Accepts multiple inputs: 8 kHz backplane clock, Loop
Timing frequencies, or 10 to 36 MHz
Locks to 8 kHz + 100 ppm (External mode)
Buffer Mode allows jitter attenuation of 10 to 36 MHz
input and x1/x0.5 or x2/x4 outputs
Exact internal ratios enable zero ppm error
Output clock rates include T1, E1, T3, E3, ISDN, xDSL,
and the OC3 submultiples
See also the MK2049-36 and MK2049-45
C
RYSTAL
2
C
C
8
LOCK
LOCK
K
H
Z
(R
MK2049-34
O
O
EGENERATED
UTPUT
UTPUT
DATASHEET
MK2049-34
/ 2
REV F 102203
)

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mk2049-34 Summary of contents

Page 1

... All outputs are frequency locked together and to the input. This part also has a jitter-attenuated Buffer capability. In this mode, the MK2049-34 is ideal for filtering jitter from 27 MHz video clocks or other clocks with high jitter. ICS can customize these devices for many other different frequencies ...

Page 2

... Connect the loop filter ceramic capacitors and resistor between this pin and - Connect a 10-200kΩ resistor to ground. Contact ICS at telecom@icst.com for recommended value for your application. Input Frequency select 0. Determines CLK input/outputs per table on page 3. 2 VCXO AND SYNTHESIZER Pin Description MK2049-34 REV F 102203 ...

Page 3

... The 8 kHz input clock does not need to have a 50% duty cycle; a “high” or “on” pulse as narrow acceptable. In the MK2049-34, the rising edges of CLK and CLK/2 are both aligned with the rising edge of the 8 kHz ICLK; refer to Figure 1 on page 4 for more details. ...

Page 4

... MHz and 13.5 MHz outputs. Input and Output Synchronization As shown in the tables on page 3, the MK2049-34 offers a Zero Delay feature in all selections. There is an internal feedback path between ICLK and the output clocks, providing a fixed phase relationship between the input and output, a requirement in many communication systems ...

Page 5

... MAN05 (http://www.icst.com/products/summary/man05.htm). Optional - cap see text G V resist resist Figure 2. Typical MK2049-34 Layout IDT™ / ICS™ 3.3 VOLT COMMUNICATIONS CLOCK VCXO PLL Cutout in ground and power plane. Route all traces away from this area resist ...

Page 6

... Crystal Operation The MK2049-34 operates by phase locking the input signal to a VCXO which consists of the recommended pullable VCXO crystals and the integrated VCXO oscillator circuit on the MK2049. To achieve the best performance and reliability, the layout guidelines shown on the previous page should be closely followed. ...

Page 7

... CLK to CLK/2 t 0 2 VDD/2, except 8 kHz Any clock selection 7 VCXO AND SYNTHESIZER Min. Typ. Max. Units 3.15 3.3 3. 0.8 V VDD-0.4 V 2 ± Min. Typ. Max. Units 8 kHz 150 ppm MK2049-34 REV F 102203 ...

Page 8

... MK2049-34SI MK2049-34SITR MK2049-34SI While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied ...

Page 9

... MK2049-34 3.3 VOLT COMMUNICATIONS CLOCK VCXO PLL Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales 800-345-7015 408-284-8200 Fax: 408-284-2775 Corporate Headquarters Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States 800 345 7015 +408 284 8200 (outside U.S.) © ...

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