MK2049-34SAITR

Manufacturer Part NumberMK2049-34SAITR
DescriptionIC VCXO PLL CLK SYNTH 20-SOIC
ManufacturerIDT, Integrated Device Technology Inc
TypePLL Clock Synthesizer
MK2049-34SAITR datasheet
 


Specifications of MK2049-34SAITR

PllYesInputClock
OutputClockNumber Of Circuits1
Ratio - Input:output1:3Differential - Input:outputNo/No
Frequency - Max77.76MHzDivider/multiplierYes/Yes
Voltage - Supply3.15 V ~ 3.45 VOperating Temperature-40°C ~ 85°C
Mounting TypeSurface MountPackage / Case20-SOIC
Frequency-max44.736MHzLead Free Status / RoHS StatusContains lead / RoHS non-compliant
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3.3 VOLT COMMUNICATIONS CLOCK VCXO PLL
Description
The MK2049-34A is a VCXO Phased Locked Loop (PLL)
based clock synthesizer that accepts multiple input
frequencies. With an 8 kHz clock input as a reference, the
MK2049-34A generates T1, E1, T3, E3, ISDN, xDSL, and
other communications frequencies. This allows for the
generation of clocks frequency-locked and phase-locked to
an 8 kHz backplane clock, simplifying clock synchronization
in communications systems. The MK2409-34 can also
accept a T1 or E1 input clock and provide the same output
for loop timing. All outputs are frequency locked together
and to the input.
This part also has a jitter-attenuated Buffer capability. In this
mode, the MK2049-34A is ideal for filtering jitter from 27
MHz video clocks or other clocks with high jitter.
IDT can customize these devices for many other different
frequencies.
Block Diagram
I
R
NPUT
EFERENCE
C
LOCK
(T
8
H
)
YPICALLY
K
Z
4
F
S
REQUENCY
ELECT
IDT™ 3.3 VOLT COMMUNICATIONS CLOCK VCXO PLL
Features
Packaged in 20-pin SOIC
Pb (lead) free package
3.3 V + 5% operation
Fixed I/O phase relationship on all selections
Meets the TR62411, ETS300 011, and GR-1244
specification for MTIE, Pull-in/Hold-in Range, Phase
Transients, and Jitter Generation for Stratum 3, 4, and 4E
Accepts multiple inputs: 8 kHz backplane clock, Loop
Timing frequencies, or 10 to 36 MHz
Locks to 8 kHz + 100 ppm (External mode)
Buffer Mode allows jitter attenuation of 10 to 36 MHz
input and x1/x0.5 or x2/x4 outputs
Exact internal ratios enable zero ppm error
Output clock rates include T1, E1, T3, E3, ISDN, xDSL,
and the OC3 submultiples
See the MK2049-01, -02, and -03 for more selections at
5 V
Industrial temperature range
E
P
C
XTERNAL
ULLABLE
(external loop filter)
F
VCXO-B
REQUENCY
ASED
M
PLL
ULTIPLYING
PLL
(M
C
ASTER
LOCK
G
)
ENERATOR
1
DATASHEET
MK2049-34A
RYSTAL
C
O
LOCK
UTPUT
2
C
O
LOCK
UTPUT
8
H
(R
K
Z
EGENERATED
MK2049-34A
/ 2
)
REV E 051310

MK2049-34SAITR Summary of contents

  • Page 1

    ... Buffer Mode allows jitter attenuation MHz input and x1/x0.5 or x2/x4 outputs • Exact internal ratios enable zero ppm error • Output clock rates include T1, E1, T3, E3, ISDN, xDSL, and the OC3 submultiples • See the MK2049-01, -02, and -03 for more selections • Industrial temperature range XTERNAL ...

  • Page 2

    ... Connect the loop filter ceramic capacitors and resistor between this pin and — Connect a 10-200k resistor to ground. Contact IDT for recommended value for your application. Input Frequency select 0. Determines CLK input/outputs per table on page 3. 2 VCXO AND SYNTHESIZER Pin Description MK2049-34A REV E 051310 ...

  • Page 3

    ... The 8 kHz input clock does not need to have a 50% duty cycle; a “high” or “on” pulse as narrow acceptable. In the MK2049-34, the rising edges of CLK and CLK/2 are both aligned with the rising edge of the 8 kHz ICLK; refer to Figure 1 on page 4 for more details. ...

  • Page 4

    ... In fact, the input and output clocks probably are locked and the MK2049 will have zero delay to the average position of the 8 kHz input clock. In order to see this clearly, a low jitter 8 kHz input clock is necessary. Most lab frequency sources are NOT SUITABLE for this since they have high jitter at low frequencies ...

  • Page 5

    ... VOLT COMMUNICATIONS CLOCK VCXO PLL PC Board Layout A proper board layout is critical to the successful use of the MK2049-34A. In particular, the CAP1 and CAP2 pins are very sensitive to noise and leakage (CAP2 at pin 18 is the most sensitive). Traces must be as short as possible and the two capacitors and resistor must be mounted next to the device as shown below ...

  • Page 6

    ... Crystal Operation The MK2049-34A operates by phase locking the input signal to a VCXO which consists of the recommended pullable VCXO crystals and the integrated VCXO oscillator circuit on the MK2049-34A. To achieve the best performance and reliability, the layout guidelines shown on the previous page should be closely followed. ...

  • Page 7

    ... External Mode, Note 1 ICLK t pi ICLK to ICLK CLK to CLK/2 t 0 2 VDD/2, except 8 kHz Any clock selection 7 VCXO AND SYNTHESIZER Min. Typ. Max. Units 3.15 3.3 3. 0.8 V VDD-0.4 V 2 ± Min. Typ. Max. Units 8 kHz 150 ppm MK2049-34A REV E 051310 ...

  • Page 8

    ... BASIC 0.050 BASIC 10.00 10.65 .394 .419 0.25 0.75 .010 .029 0.40 1.27 .016 .050 Package Temperature 20-pin SOIC -40 to +85 C 20-pin SOIC -40 to +85 C MK2049-34A REV E 051310 C ...

  • Page 9

    ... MK2049-34A 3.3 VOLT COMMUNICATIONS CLOCK VCXO PLL Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales 800-345-7015 408-284-8200 Fax: 408-284-2775 Corporate Headquarters Integrated Device Technology, Inc. www.idt.com © 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device Technology, Inc ...