MK2049-45SILFTR

Manufacturer Part NumberMK2049-45SILFTR
DescriptionIC CLK PLL COMM 3.3V 20-SOIC
ManufacturerIDT, Integrated Device Technology Inc
TypePLL Clock Synthesizer
MK2049-45SILFTR datasheet
 


Specifications of MK2049-45SILFTR

PllYesInputClock
OutputClockNumber Of Circuits1
Ratio - Input:output1:3Differential - Input:outputNo/No
Frequency - Max49.152MHzDivider/multiplierYes/Yes
Voltage - Supply3.15 V ~ 3.45 VOperating Temperature-40°C ~ 85°C
Mounting TypeSurface MountPackage / Case20-SOIC
Frequency-max49.152MHzLead Free Status / RoHS StatusLead free / RoHS Compliant
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3.3 VOLT COMMUNICATIONS CLOCK PLL
Description
The MK2049-45 is a dual Phase-Locked Loop (PLL) device
which can provide frequency synthesis and jitter
attenuation. The first PLL is VCXO based and uses a
pullable crystal to track signal wander and attenuate input
jitter. The second PLL is a translator for frequency
multiplication. Basic configuration is determined by a
Mode/Frequency Selection Table. Loop bandwidth and
damping factor are programmable via external loop filter
component selection.
Buffer Mode accepts a 10 to 50MHz input and will provide a
jitter attenuated output at 0.5 x ICLK, 1 x ICLK or 2 x ICLK.
In this mode the MK2049-45 is ideal for filtering jitter from
high frequency clocks.
In External Mode, ICLK accepts an 8 kHz clock and will
produce output frequencies from a table of common
communciations clock rates, CLK and CLK/2. This allows
for the generation of clocks frequency-locked to an 8 kHz
backplane clock, simplifying clock synchronization in
communications systems.
The MK2049-45 can be dynamically switched between T1,
E1, T3, E3 outputs with the same 24.576 MHz crystal.
ICS can customize these devices for many other different
frequencies. Contact your ICS representative for more
details.
Block Diagram
C
S
R
C
SET
P
R
S
ISET
CAP2
Phase
Reference
Detector
Divider
ICLK
(used in buffer
mode only)
VCXO
PLL
4
Divider Value
FS3:0
Look-up Table
IDT™ / ICS™ 3.3 VOLT COMMUNICATIONS CLOCK PLL
Features
Packaged in 20 pin SOIC
3.3 V + 5% operation
Meets the TR62411, ETS300 011, and GR-1244
specification for MTIE, Pull-in/Hold-in Range, Phase
Transients, and Jitter Generation for Stratum 3, 4, and 4E
Accepts multiple inputs: 8 kHz backplane clock, or 10 to
50 MHz
Locks to 8 kHz + 100 ppm (External mode)
Buffer Mode allows jitter attenuation of 10 - 50 MHz input
and x1 / x0.5 or x1 / x2 outputs
Exact internal ratios enable zero ppm error
Output rates include T1, E1, T3, E3, and OC3
submultiples
Available in Pb (lead) free package
See also the MK2049-34 and MK2049-36
Not recommended for new designs. Use the
MK2049-45A.
C
C
Optional Crystal Load Caps
L
L
External Pullable Crystal
CAP1
X1
X2
Reference
VCXO
Divider
Charge
Pump
Feedback
Divider (N)
Translator
PLL
1
DATASHEET
MK2049-45
Output
VCO
Divider
Divide
by 2
Feedback
Divider
MK2049-45
CLK
CLK/2
8k
REV G 101904

MK2049-45SILFTR Summary of contents

  • Page 1

    ... Buffer Mode accepts 50MHz input and will provide a jitter attenuated output at 0.5 x ICLK ICLK ICLK. In this mode the MK2049-45 is ideal for filtering jitter from high frequency clocks. In External Mode, ICLK accepts an 8 kHz clock and will produce output frequencies from a table of common communciations clock rates, CLK and CLK/2 ...

  • Page 2

    ... Input clock connection. Connect to 8 kHz backplane or MHz clock. Power Connect to ground. Power Power Supply. Connect to +3.3V. Loop Connect the loop filter capacitors and resistor between this pin and CAP2. Filter Power Connect to ground. 2 VCXO AND SYNTHESIZER Pin Description MK2049-45 REV G 101904 ...

  • Page 3

    ... Output Clock Selection Table on Page 2. Most typical PLL clock devices use an internal VCO (Voltage Controlled Oscillator) for output clock generation. By using a VCXO with an external crystal, the MK2049-45 is able to generate a low jitter, low phase-noise output clock within a 3 VCXO AND SYNTHESIZER ...

  • Page 4

    ... Please refer to the Quartz Crystal section on this page regarding external crystal requirements. Quartz Crystal It is important that the correct type of quartz crystal is used with the MK2049-45. Failure may result in reduced frequency pullability range, inability of the loop to lock, or excessive output phase jitter. The MK2049-45 operates by phase-locking the VCXO circuit to the input signal of the selected ICLK input ...

  • Page 5

    ... VDD and the PCB ground plane. To further guard against interfering system supply noise, the MK2049-45 should use one common connection to the PCB power plane as shown in the diagram on the next page. The ferrite bead and bulk capacitor help reduce lower frequency noise in the supply that can lead to output clock phase IDT™ ...

  • Page 6

    ... An optimum layout is one with all components on the Absolute Maximum Ratings Stresses above the ratings listed below can cause permanent damage to the MK2049-45. These ratings, which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied ...

  • Page 7

    ... MHz t Referenced to jf Mitel/Zarlink MT9045, Note 3 7 VCXO AND SYNTHESIZER Min. Typ. Max. Units 3.15 3.3 3. 0.8 V µA -10 +10 µA -10 + VDD-0.4 V 2.4 V 0.4 V ± VDD V Min. Typ. Max. Units -115 +115 ppm 0 1 400 ps MK2049-45 REV G 101904 ...

  • Page 8

    ... If controlled input to output skew is desired for this output clock frequency please refer to the MK2049 or MK2069 products. Note 3: Input reference is the 8 kHz output from a Mitel/Zarlink MT9045 device in freerun mode (SEL2:0 = 100, 19 ...

  • Page 9

    ... MK2049-45SITR MK2049-45SI MK2049-45SILF MK2049-45SILF MK2049-45SILFTR MK2049-45SILF “LF” denotes Pb (lead) free package. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied ...

  • Page 10

    ... MK2049-45 3.3 VOLT COMMUNICATIONS CLOCK PLL Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales 800-345-7015 408-284-8200 Fax: 408-284-2775 Corporate Headquarters Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States 800 345 7015 +408 284 8200 (outside U.S.) © ...