MK2049-34SAILF IDT, Integrated Device Technology Inc, MK2049-34SAILF Datasheet
MK2049-34SAILF
Specifications of MK2049-34SAILF
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MK2049-34SAILF Summary of contents
Page 1
... Buffer Mode allows jitter attenuation MHz input and x1/x0.5 or x2/x4 outputs • Exact internal ratios enable zero ppm error • Output clock rates include T1, E1, T3, E3, ISDN, xDSL, and the OC3 submultiples • See the MK2049-01, -02, and -03 for more selections • Industrial temperature range XTERNAL ...
Page 2
... Connect the loop filter ceramic capacitors and resistor between this pin and — Connect a 10-200k resistor to ground. Contact IDT for recommended value for your application. Input Frequency select 0. Determines CLK input/outputs per table on page 3. 2 VCXO AND SYNTHESIZER Pin Description MK2049-34A REV E 051310 ...
Page 3
... The 8 kHz input clock does not need to have a 50% duty cycle; a “high” or “on” pulse as narrow acceptable. In the MK2049-34, the rising edges of CLK and CLK/2 are both aligned with the rising edge of the 8 kHz ICLK; refer to Figure 1 on page 4 for more details. ...
Page 4
... In fact, the input and output clocks probably are locked and the MK2049 will have zero delay to the average position of the 8 kHz input clock. In order to see this clearly, a low jitter 8 kHz input clock is necessary. Most lab frequency sources are NOT SUITABLE for this since they have high jitter at low frequencies ...
Page 5
... VOLT COMMUNICATIONS CLOCK VCXO PLL PC Board Layout A proper board layout is critical to the successful use of the MK2049-34A. In particular, the CAP1 and CAP2 pins are very sensitive to noise and leakage (CAP2 at pin 18 is the most sensitive). Traces must be as short as possible and the two capacitors and resistor must be mounted next to the device as shown below ...
Page 6
... Crystal Operation The MK2049-34A operates by phase locking the input signal to a VCXO which consists of the recommended pullable VCXO crystals and the integrated VCXO oscillator circuit on the MK2049-34A. To achieve the best performance and reliability, the layout guidelines shown on the previous page should be closely followed. ...
Page 7
... External Mode, Note 1 ICLK t pi ICLK to ICLK CLK to CLK/2 t 0 2 VDD/2, except 8 kHz Any clock selection 7 VCXO AND SYNTHESIZER Min. Typ. Max. Units 3.15 3.3 3. 0.8 V VDD-0.4 V 2 ± Min. Typ. Max. Units 8 kHz 150 ppm MK2049-34A REV E 051310 ...
Page 8
... MK2049-34SAILF MK2049-34SAILF MK2049-34SAILFTR MK2049-34SAILF "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied ...
Page 9
... MK2049-34A 3.3 VOLT COMMUNICATIONS CLOCK VCXO PLL Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales 800-345-7015 408-284-8200 Fax: 408-284-2775 Corporate Headquarters Integrated Device Technology, Inc. www.idt.com © 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device Technology, Inc ...