P87LPC767 NXP Semiconductors, P87LPC767 Datasheet
P87LPC767
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P87LPC767 Summary of contents
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... P87LPC767 Low power, low price, low pin count (20 pin) microcontroller with 4-kbyte OTP and 8-bit A/D converter Product data Supersedes data of 2001 Aug 07 hilips Semiconductors INTEGRATED CIRCUITS 2002 Mar 25 ...
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... Product data P87LPC767 ...
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... Product data P87LPC767 ...
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... The P87LPC767 is a 20-pin single-chip microcontroller designed for low pin count applications demanding high-integration, low cost solutions over a wide range of performance requirements. A member of the Philips low pin count family, the P87LPC767 offers programmable oscillator configurations for high and low speed crystals or RC operation, wide operating voltage range, programmable port output configurations, selectable Schmitt trigger inputs, LED drive outputs, and a built-in watchdog timer ...
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... P87LPC767FN DIP20 plastic dual in-line package; 20 leads (300 mil) P87LPC767FD SO20 plastic small outline package; 20 leads; body width 7.5 mm P87LPC767HD SO20 plastic small outline package; 20 leads; body width 7.5 mm PIN CONFIGURATION, 20-PIN DIP AND SO PACKAGES LOGIC SYMBOL CMP2 CIN2B ...
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... CONFIGURABLE I/OS PORT 1 CONFIGURABLE I/OS PORT 0 CONFIGURABLE I/OS KEYPAD INTERRUPT CONFIGURABLE CRYSTAL OR OSCILLATOR RESONATOR 2002 Mar 25 ACCELERATED 80C51 CPU INTERNAL BUS TIMER 0, 1 WATCHDOG TIMER AND OSCILLATOR ANALOG COMPARATORS CONVERTER ON-CHIP POWER MONITOR RC (POWER-ON RESET, OSCILLATOR BROWNOUT RESET) 3 Product data P87LPC767 UART A/D SU01351 ...
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... MEMORY SPACE * The 87LPC767 does not support access to external data memory. However, the User Configuration Bytes are accessed via the MOVX instruction as if they were in external data memory. Figure 1. P87LPC767 Program and Data Memory Map 2002 Mar 25 FFh SPECIAL FUNCTION REGISTERS ...
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... RST External Reset input (if selected via EPROM configuration). A low on this pin resets the microcontroller, causing I/O ports and peripherals to take on their default states, and the processor begins execution at address 0. When used as a port pin, P1 Schmitt trigger input only. 5 Product data P87LPC767 ...
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... EBO E8h ETI – EC1 EAD B8h – PWD PBO PS B7h – PWDH PBOH PSH 6 Product data P87LPC767 Reset Value LSB 00h ADCS RCCLK AADR1 AADR0 00h 1 SRST 0 – DPS 02h ...
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... TF1 TR1 TF0 TR0 8Ch 8Dh 8Ah 8Bh 89h GATE C A7h – – WDOVF WDRUN A6h 7 Product data P87LPC767 Reset Value LSB – PC2 PKB PI2 00h 1 – PC2H PKBH PI2H 00h 00h CIN1B ...
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... The P87LPC767 uses an enhanced 80C51 CPU which runs at twice the speed of standard 80C51 devices. This means that the performance of the P87LPC767 running at 5 MHz is exactly the same as that of a standard 80C51 running at 10 MHz. A machine cycle consists of 6 oscillator cycles, and most instructions execute clocks ...
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... Table 1. In Table 1, maximum times for RCCLK = 1 use an RC clock frequency of 4.5 MHz (6 MHz - 25%). Minimum times for RCCLK = 1 use an RC clock frequency of 7.5 MHz (6 MHz + 25%). Nominal time assume an ideal RC clock frequency of 6 MHz and an average of 3.5 machine cycles at the CPU clock rate. 9 Product data P87LPC767 RCCLK AADR1 ...
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... A/D accuracy is also affected by noise generated elsewhere in the application, power supply noise, and power supply regulation. Since the P87LPC767 power pins are also used as the A/D reference and supply, the power supply has a very direct affect on the accuracy of A/D readings. Using the A/D without Power Down mode while the clock is divided through the use of CLKR or DIVM has an adverse effect on A/D accuracy ...
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... Get A/D result, ; and save it in memory. ; Clear the A/D completion flag. ; Clear the A/D channel number. ; Restore accumulator. ; Add in the new channel number. ; Start A/D conversion. ; Wait for ADCI to be set. ; Get A/D result. ; Clear the A/D completion flag. ; Clear the A/D channel number. 11 Product data P87LPC767 ...
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... Low power, low price, low pin count (20 pin) microcontroller with 4-kbyte OTP and 8-bit A/D converter Analog Comparators Two analog comparators are provided on the P87LPC767. Input and output options allow use of the comparators in a number of different configurations. Comparator operation is such that the output is a ...
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... COn CMPREF CINnA COn V (1.23V) ref CINnB COn CMPREF CINnB COn V (1.23V) ref Figure 6. Comparator Configurations 13 Product data P87LPC767 CMP1 (P0.6) CMF1 INTERRUPT CMP2 (P0.0) CMF2 INTERRUPT SU01153 CPn, CNn, OEn = COn CMPn – CPn, CNn, OEn = COn CMPn – CPn, CNn, OEn = ...
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... Output to CMP1 pin enabled. ; The comparator has to start up for at ; least 10 microseconds before use. ; Clear comparator 1 interrupt flag. ; Enable the comparator 1 interrupt. The ; priority is left at the current value. ; Enable the interrupt system (if needed). ; Return to caller. Figure 7. 14 Product data P87LPC767 SU01189 ...
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... The first five of these times are 4.7 ms (see I are covered by the low order three bits of timer I. Timer I is clocked by the P87LPC767 CPU clock. Timer I can be pre-loaded with one of four values to optimize timing for different oscillator frequencies. At lower frequencies, software response time is increased and will degrade maximum performance of the I register I2CFG description for prescale values (CT0, CT1) ...
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... STR, or STP is set, clearing DRDY will not release SCL to high that the I C will not the next bit program detects ATN = 1, and DRDY = 0, it should examine ARL, STR, and STP. 16 Product data P87LPC767 Reset Value: 81h 1 0 — XSTR XSTP 2 ...
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... XDAT = 0; it sets Transmit Active and drives SDA low during the SCL low time. After SCL goes high, the I hardware waits for the suitable minimum time and then releases SDA to high to make the stop condition. 17 Product data P87LPC767 2 C interface will only drive 2 C hardware to 2 ...
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... SCL when this device is a master on the I controls both of these parameters, and also the timing for stop and start conditions. Regarding Software Response Time Because the P87LPC767 can run at 20 MHz, and because the I interface is optimized for high-speed operation quite likely that 2 ...
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... Interrupts The P87LPC767 uses a four priority level interrupt structure. This allows great flexibility in controlling the handling of the P87LPC767’s many interrupt sources. The P87LPC767 supports interrupt sources. Each interrupt source can be individually enabled or disabled by setting or clearing a bit in registers IEN0 or IEN1. The IEN0 register also contains a global disable bit, EA, which disables all interrupts at once ...
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... IEn when the interrupt is level sensitive, it simply tracks the input pin level external interrupt is enabled when the P87LPC767 is put into Power Down or Idle mode, the interrupt will cause the processor to wake up and resume operation. Refer to the section on Power Reduction Modes for details ...
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... Low power, low price, low pin count (20 pin) microcontroller with 4-kbyte OTP and 8-bit A/D converter I/O Ports The P87LPC767 has 3 I/O ports, port 0, port 1, and port 2. The exact number of I/O pins available depend upon the oscillator and reset options chosen. At least 15 pins of the P87LPC767 may be used as I/Os when a two-pin external oscillator and an external reset circuit are used ...
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... The last two functions are described in the Timer/Counters and Oscillator sections respectively. The enable bits for all of these functions are shown in Figure 15. Each I/O port of the P87LPC767 may be selected to use TTL level inputs or Schmitt inputs with hysteresis. A single configuration bit determines this selection for the entire port. Port pins P1.2, P1.3, and P1 ...
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... P0S When P0S = 1, this bit enables Schmitt trigger inputs on Port 0. P2M1.4 ENCLK When ENCLK is set and the P87LPC767 is configured to use the on-chip RC oscillator, a clock output is enabled on the X2 pin (P2.0). Refer to the Oscillator section for details. P2M1.3 ENT1 When set, the P.7 pin is toggled whenever Timer 1 overflows. The output frequency is therefore one half of the Timer 1 overflow rate ...
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... Note: the Keyboard Interrupt must be enabled in order for the settings of the KBI register to be effective. The interrupt flag (KBF) is located at bit 7 of AUXR1. 2002 Mar 25 EKB (FROM IEN1 REGISTER) Figure 16. Keyboard Interrupt KBI.5 KBI.4 KBI.3 KBI.2 KBI.1 Figure 17. Keyboard Interrupt Register (KBI) 24 Product data P87LPC767 KBF (KBI INTERRUPT) SU01163 Reset Value: 00h 1 0 KBI.0 SU01164 ...
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... A clock output on the X2/P2.0 pin may be enabled when the external clock input is used. Clock Output The P87LPC767 supports a clock output function when either the on-chip RC oscillator or external clock input options are selected. This allows external devices to synchronize to the P87LPC767. ...
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... A CLOCK OUTPUT MAY BE OBTAINED ON THE X2 PIN BY SETTING THE ENCLK BIT IN THE P2M1 REGISTER. 2002 Mar 25 QUARTZ CRYSTAL OR CERAMIC RESONATOR Figure 18. Using the Crystal Oscillator CMOS COMPATIBLE EXTERNAL OSCILLATOR SIGNAL Figure 19. Using an External Clock Input 26 Product data P87LPC767 87LPC767 SU01357 87LPC767 X1 X2 SU01358 ...
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... P87LPC767 instruction and peripheral timing to match standard 80C51 timing by dividing the CPU clock by two. Default timing for the P87LPC767 is 6 CPU clocks per machine cycle while standard 80C51 timing is 12 clocks per machine cycle. This division also applies to peripheral timing, allowing 80C51 code that is oscillator frequency and/or timer rate dependent ...
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... When this feature is activated, the POF flag in the PCON register is set to indicate an initial power up condition. The POF flag will remain set until cleared by software. Power Reduction Modes The P87LPC767 supports Idle and Power Down modes of power reduction. Idle Mode The Idle mode leaves peripherals running in order to allow them to activate the processor when an interrupt is generated ...
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... The corresponding interrupt must be enabled. Reset Input The external reset input must be enabled. A/D converter Must use internal RC clock (RCCLK = 1) for A/D converter to work in Power Down mode. The A/D must be enabled and properly set up. The corresponding interrupt must be enabled. 2002 Mar 25 29 Product data P87LPC767 ...
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... While the signal on the RST pin is less than low, the P87LPC767 is held in reset until the signal goes high. The watchdog timer on the P87LPC767 can act as an oscillator fail detect because it uses an independent, fully on-chip oscillator. UCFG1 is described in the System Configuration Bytes section of this datasheet. ...
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... Low power, low price, low pin count (20 pin) microcontroller with 4-kbyte OTP and 8-bit A/D converter Timer/Counters The P87LPC767 has two general purpose counter/timers which are upward compatible with the standard 80C51 Timer 0 and Timer 1. Both can be configured to operate either as timers or event counters (see Figure 24) ...
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... Figure 26. There are two different GATE bits, one for Timer 1 (TMOD.7) and one for Timer 0 (TMOD.3 TF0 TR0 IE1 IT1 IE0 TLn THn (5 BITS) (8 BITS) CONTROL TOGGLE 32 Product data P87LPC767 Reset Value: 00h 0 IT0 SU01172 OVERFLOW TFn INTERRUPT Tn PIN TnOE SU01173 ...
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... Mode 3 is provided for applications that require an extra 8-bit timer. With Timer 0 in Mode 3, an P87LPC767 can look like it has three Timer/Counters. When Timer Mode 3, Timer 1 can be turned on and off by switching it into and out of its own Mode 3. It can still be used by the serial port as a baud rate generator any application not requiring an interrupt ...
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... The port outputs will be a logic 1 prior to the first timer overflow when this mode is turned on. UART The P87LPC767 includes an enhanced 80C51 UART. The baud rate source for the UART is timer 1 for modes 1 and 3, while the rate is fixed in modes 0 and 2. Because CPU clocking is different on the P87LPC767 than on the standard 80C51, baud rate calculation is somewhat different ...
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... SM2 REN TB8 RB8 Baud Rate CPU clock/6 Variable (see text) CPU clock/32 or CPU clock/16 Variable (see text) Figure 30. Serial Port Control Register (SCON) 35 Product data P87LPC767 Reset Value: 00h SU01157 ...
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... Product data P87LPC767 CPU clock frequency 192 ( SMOD1 + 1) 256 * (TH1) 38.4k 57.6k * 7.3728 * 11.0592 * 14.7456 – – – – – – – – – – ...
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... Product data P87LPC767 57.6k 115.2k 5.5296 * 11.0592 * 11.0592 – 16.5888 – – – – – – – – – – – – – ...
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... Ten bits are transmitted (through TxD), or received (through RxD): a start bit (0), 8 data bits (LSB first), and a stop bit (1). On receive, the stop bit goes into RB8 in SCON. In the P87LPC767 the baud rate is determined by the Timer 1 overflow rate. Figure 32 shows a simplified functional diagram of the serial port in Mode 1, and associated timings for transmit receive ...
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... INTERNAL BUS S1 ... S6 S1 ... S6 S1 ... S6 S1 ... S6 S1 ... S6 S1 ... Figure 31. Serial Port Mode 0 39 Product data P87LPC767 RxD P1.1 ALT OUTPUT FUNCTION TxD P1.0 ALT OUTPUT FUNCTION SHIFT CLOCK RXD P1.1 ALT INPUT FUNCTION S1 ... S6 S1 ... S6 S1 ... S6 TRANSMIT D7 RECEIVE D6 ...
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... INPUT SHIFT REGISTER DETECTOR LOAD SBUF SBUF READ SBUF 80C51 INTERNAL BUS Figure 32. Serial Port Mode 1 40 Product data P87LPC767 TxD P1.0 ALT OUTPUT FUNCTION SERIAL PORT INTERRUPT TRANSMIT D6 D7 STOP BIT D6 D7 STOP BIT RECEIVE SU01179 ...
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... SM2 has no effect in Mode 0, and in Mode 1 can be used to check the validity of the stop bit, although this is better done with the Framing Error flag Mode 1 reception, if SM2 = 1, the receive interrupt will not be activated unless a valid stop bit is received. 41 Product data P87LPC767 ...
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... INPUT SHIFT REGISTER LOAD SBUF SBUF READ SBUF 80C51 INTERNAL BUS Figure 33. Serial Port Mode 2 42 Product data P87LPC767 TxD P1.0 ALT OUTPUT FUNCTION SERIAL PORT INTERRUPT TRANSMIT D6 D7 TB8 STOP BIT D6 D7 RB8 STOP BIT RECEIVE SU01180 ...
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... INPUT SHIFT REGISTER DETECTOR LOAD SBUF SBUF READ SBUF 80C51 INTERNAL BUS Figure 34. Serial Port Mode 3 43 Product data P87LPC767 TxD P1.0 ALT OUTPUT FUNCTION SERIAL PORT INTERRUPT TRANSMIT D6 D7 TB8 STOP BIT D6 D7 RB8 STOP BIT RECEIVE SU01181 ...
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... If the CPU clock was still running, code execution will begin immediately after that. If the processor was in Power Down mode, the watchdog reset will start the oscillator and code execution will resume after the oscillator is stable. 44 Product data P87LPC767 ...
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... Minimum Time Nominal Time 131 ms 165 ms 262 ms 330 ms 524 ms 660 ms 1.05 sec 1.3 sec 2.1 sec 45 Product data P87LPC767 WATCHDOG RESET WATCHDOG INTERRUPT WDTE (UCFG1.7) S WDOVF Q (WDCON.5) R SU01635 1 0 WDS0 Maximum Time 180 ms 360 ms 719 ms 1 ...
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... See the Power Reduction Modes section for details. AUXR1.3 SRST Software Reset. When set by software, resets the P87LPC767 hardware reset occurred. AUXR1.2 — This bit contains a hard-wired 0. Allows toggling of the DPS bit by incrementing AUXR1, without interfering with other bits in the register ...
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... UCFG bytes are programmed. System Configuration Bytes A number of user configurable features of the P87LPC767 must be defined at power up and therefore cannot be set by the program after start of execution. Those features are configured through the use of two EPROM bytes that are programmed in the same manner as the EPROM program space ...
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... Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless otherwise noted. 2002 Mar — — — — — Protection Description 48 Product data P87LPC767 Unprogrammed Value: FFh 0 — SU01186 RATING UNIT –55 to +125 C –65 to +150 +11.0 V –0 +0.5 V ...
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... MHz or less are guaranteed to continue to execute instructions correctly OSC = 2 not guaranteed +70 C, – + – +125 C, unless otherwise specified amb 49 Product data P87LPC767 LIMITS UNIT UNIT 1,2 MIN TYP MAX ...
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... A source impedance higher than this driving an A/D input may result in loss of precision and erroneous readings. 2002 Mar 25 TEST CONDITIONS TEST CONDITIONS 1 0 < V < TEST CONDITIONS TEST CONDITIONS A/D enabled 100 kHz 50 Product data P87LPC767 LIMITS UNIT UNIT MIN TYP MAX –0 –50 dB 250 ...
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... Center of a step of the actual transfer curve. 2002 Mar 25 (2) (1) (5) (4) (3) 1 LSB (ideal) 250 251 (LSB ) IN ideal 1 LSB = ). e Figure 40. A/D Conversion Characteristics 51 Product data P87LPC767 Offset Gain error error 252 253 254 255 256 256 SU01355 ...
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... Parts are guaranteed to operate down to 0 Hz. 4. Applies only to an external clock source, not when a crystal is connected to the X1 and X2 pins. 2002 Mar 6.0 V unless otherwise specified PARAMETER PARAMETER = Product data P87LPC767 LIMITS UNIT UNIT MIN MAX 0 20 MHz 0 ...
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... DD – 0 CHCL CLCX t C Figure 42. External Clock Timing 1000 6.0 V 5.0 V 100 4.0 V 3 100 100 SU01202 Figure 44. Typical Idd versus frequency (medium frequency 53 Product data P87LPC767 SET TI VALID VALID VALID SET RI SU01187 t CHCX t CLCH SU01188 6.0 V 6.0 V 5.0 V 5.0 V 4.0 V 3.3 V 2.7 V 2.7 V 1,000 ...
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... Figure 48. Typical Idle Idd versus frequency (external clock, 10,000 5.0 V 4.0 V 3.3 V 1,000 2.7 V 100 10 10,000 100,000 10 SU01205 Figure 49. Typical Idle Idd versus frequency (external clock, 4.0 V 3.3 V 2.7 V 10,000 SU01206 54 Product data P87LPC767 4.0 V 3.3 V 2.7 V 100 1,000 10,000 Frequency (kHz) SU01207 25 C, LPEP = 1) 5.0 V 4.0 V 6.0 V 3.3 V 2.7 V 100 1,000 10,000 100,000 Frequency (kHz) SU01208 ...
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... Philips Semiconductors Low power, low price, low pin count (20 pin) microcontroller with 4-kbyte OTP and 8-bit A/D converter DIP20: plastic dual in-line package; 20 leads (300 mil) 2002 Mar 25 55 Product data P87LPC767 SOT146-1 ...
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... Philips Semiconductors Low power, low price, low pin count (20 pin) microcontroller with 4-kbyte OTP and 8-bit A/D converter SO20: plastic small outline package; 20 leads; body width 7.5 mm 2002 Mar 25 56 Product data P87LPC767 SOT163-1 ...
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... Low power, low price, low pin count (20 pin) microcontroller with 4-kbyte OTP and 8-bit A/D converter REVISION HISTORY Date CPCN 2002 Mar 25 9397 750 09557 2001 Aug 07 9397 750 08675 2002 Mar 25 Description – Added revision history – Updated Reset section Previous release 57 Product data P87LPC767 ...
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... Mar components conveys a license under the Philips’ system provided the system conforms to the Fax: + 24825 Document order number: 58 Product data P87LPC767 2 C patent Koninklijke Philips Electronics N.V. 2002 All rights reserved. Printed in U.S.A. Date of release: 03-02 9397 750 09557 ...