pca9541a NXP Semiconductors, pca9541a Datasheet
pca9541a
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pca9541a Summary of contents
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... The pass gates of the switches are constructed such that the V the maximum high voltage, which will be passed by the PCA9541A. This allows the use of different bus voltages on each pair, so that 1 3.3 V devices can communicate with 5 V devices without any additional protection. ...
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... NXP Semiconductors An active LOW reset input allows the PCA9541A to be initialized. Pulling the RESET pin LOW resets the I does the internal Power-On Reset (POR) function. 2. Features I 2-to-1 bidirectional master selector C-bus interface logic; compatible with SMBus standards I PCA9541A/01 powers up with Channel 0 selected ...
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... NXP Semiconductors 4. Ordering information Table 1. Ordering information +85 C amb Type number Package Name PCA9541AD/01 SO16 PCA9541APW/01 TSSOP16 PCA9541ABS/01 HVQFN16 PCA9541AD/03 SO16 PCA9541APW/03 TSSOP16 PCA9541ABS/03 HVQFN16 5. Marking Table 2. Type number PCA9541AD/01 PCA9541APW/01 PCA9541ABS/01 PCA9541AD/03 PCA9541APW/03 PCA9541ABS/03 PCA9541A_3 Product data sheet ...
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... PCA9541A SCL_MST0 SDA_MST0 RESET POWER-ON RESET V DD SCL_MST1 SDA_MST1 INT0 INT1 Fig 1. Block diagram of PCA9541A PCA9541A_3 Product data sheet 2 2-to-1 I C-bus master selector with interrupt logic and reset INPUT STOP FILTER DETECTION 2 I C-BUS CONTROL AND REGISTER BANK INPUT ...
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... SDA_MST1 Fig 3. terminal 1 index area 1 12 SCL_MST0 RESET 2 11 PCA9541ABS/01 PCA9541ABS/ SCL_MST1 4 9 SDA_MST1 Transparent top view Rev. 03 — 16 July 2009 PCA9541A 1 16 INT0 PCA9541APW/01 PCA9541APW/ INT1 002aae658 Pin configuration for TSSOP16 ...
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... For enhanced thermal, electrical, Rev. 03 — 16 July 2009 PCA9541A Description active LOW interrupt output 0 (external pull-up required) serial data master 0 (external pull-up required) serial clock master 0 (external pull-up required) active LOW reset input (external pull-up required) ...
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... Command Code Following the successful acknowledgement of the slave address, the bus master will send a byte to the PCA9541A, which will be stored in the Command Code register. Fig 6. The 2 LSBs are used as a pointer to determine which register will be accessed. ...
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... NXP Semiconductors • During a write operation, the PCA9541A will acknowledge bytes sent to the IE and CONTROL registers, but will not acknowledge a byte sent to the Interrupt Status Register since read-only register. The 2 LSBs of the Command Code do not roll over to 00b but stay at 10b. ...
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... SDA line because the PCA9541A did not acknowledge the last byte. 3. When the initialization has been requested and completed, the PCA9541A sends an interrupt to the new master through its INT line and connects the new master to the downstream channel ...
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... INT will not be generated when a non-idle situation has been detected on the downstream slave channel by the bus sensor at the switching moment (masked). Remark: Channel switching is done automatically after the STOP command. Rev. 03 — 16 July 2009 PCA9541A 2 1 BUSOKMSK BUSINITMSK © ...
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... INTINMSK R/W [1] Default values are the same for PCA9541A/01, PCA9541A/03. 8.3.2 Register 1: Control Register (B1:B0 = 01b) The Control Register described below is identical for both the masters. Nevertheless, there are physically 2 internal Control Registers, one for each upstream channel. When master 0 reads/writes in this register, the internal Control Register 0 will be accessed. ...
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... When both masters request a switch to their own channel at the same time, the master who last wrote to its Control Register before the PCA9541A receives a STOP command wins the switching sequence. There is no arbitration performed. The Auto Increment feature ( allows to program the PCA9541A in 4 bytes: Start 111A3A2A1A0 + 0 ...
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... NXP Semiconductors Table 11. Default Control Register values Type version Master Bit 7 NTESTON TESTON PCA9541A/01 MST_0 0 MST_1 0 PCA9541A/03 MST_0 0 MST_1 0 Table 12 master device wants to take control of the I function of the current I Control Register. Current status of the I NBUSON is one of the following: • The master reading its Control Register does not have control and the I • ...
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Table 12. Bus control sequence Read Control Register performed by the master Byte Status NBUSON BUSON NMYBUS MYBUS Byte [1] read Hex 0 bus off has control bus off no control bus off no ...
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... The bus recovery/initialization has been performed and that the downstream channel connection has been done (built-in bus recovery/initialization active). – A ‘bus not well initialized’ condition has been detected by the PCA9541A when the switch has been done (built-in bus recovery/initialization not active). This information can be used by the new master to initiate its own bus recovery/initialization sequence ...
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... Rev. 03 — 16 July 2009 PCA9541A BUSOK BUSINIT [3] [3] [3] [3] © NXP B.V. 2009. All rights reserved. ...
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... PCA9541A in a reset DD has reached this point, the reset condition is released and the DD POR must be lowered below 0 reset the device. ...
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... Pass gate voltage as a function of supply voltage shows the voltage characteristics of the pass gate transistors (note that the graph will be at 3.3 V when the PCA9541A supply voltage is 3 lower so the 2 C/SMBus multiplexers and switches . Rev. 03 — 16 July 2009 PCA9541A 2 C-bus downstream channel for the ...
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... C-bus master selector with interrupt logic and reset 2 C-bus SDA SCL data line stable; data valid Bit transfer Figure 10). SDA SCL S START condition Rev. 03 — 16 July 2009 PCA9541A Figure 9). change of data allowed mba607 P STOP condition © NXP B.V. 2009. All rights reserved. mba608 ...
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... SLAVE SLAVE TRANSMITTER/ RECEIVER TRANSMITTER RECEIVER data output by transmitter data output by receiver SCL from master 1 S START condition 2 C-bus Rev. 03 — 16 July 2009 PCA9541A 11). MASTER MASTER TRANSMITTER/ MULTIPLEXER RECEIVER SLAVE not acknowledge acknowledge 2 8 clock pulse for acknowledgement 2 I C-BUS 002aaa966 ...
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... START condition R/W acknowledge from slave Fig 13. Write to the Interrupt Enable and Control registers using the Auto-Increment (AI) bit Remark third data byte is sent, it will not be acknowledged by the PCA9541A. slave address START condition ( 00: Interrupt Enable register ...
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SDA_MST0 slave address command code register START condition R/W auto increment acknowledge from slave SCL_MST0 INT1 SCL_SLAVE SDA_SLAVE INT0 MASTER 1 ...
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... MASTER 0 must wait for the 'bus free time' value (between STOP and START) defined in the I before sending commands to the downstream devices. Rev. 03 — 16 July 2009 PCA9541A After the STOP condition MASTER 1 is disconnected from the downstream channel, and MASTER 0 is connected to the downstream channel ...
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... I required even if one master fails or its controller card is removed for maintenance. The PCA9541A can also be used in other applications, such as where masters share the same resource but cannot share the same bus gatekeeper multiplexer in long single bus applications bus initialization/recovery device. ...
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... Fig 19. Very high reliability backplane application PCA9541A_3 Product data sheet 2 2-to-1 I C-bus master selector with interrupt logic and reset Figure 2 C-bus slave cards/devices via a PCA9541A/01 for non-hot swap SCL0 SDA0 2 C-bus. Either master at any time can gain control of the slave devices if Figure 19. SCL0 ...
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... NXP Semiconductors 10.3 Masters with shared resources Some masters may not be multi-master capable or some masters may not work well together and continually lock up the bus. The PCA9541A can be used to separate the masters, as shown in Field Replaceable Unit (FRU) EEPROMs or temperature sensors. Fig 20. Masters with shared resources application 10 ...
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... C-bus is hung, I and Slave 2 in PCA9541A/03 disconnects the bus when it is reset via the hardware reset line, restoring the master's control of the rest of the bus (for example, Slave 0). The bus master can then command the PCA9541A/03 to send 9 clock pulses/STOP condition to reset the downstream I downstream devices isolated ...
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... DD SS SCL load Rev. 03 — 16 July 2009 PCA9541A [1] Conditions Min 0.5 0 100 100 - 60 operating in free air 40 Min Typ 2 152 - 349 - [1] - 1.5 0 ...
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... 100 A i(sw) DD o(sw 3 3.6 V; i(sw 100 A o(sw 2 100 A i(sw) DD o(sw 2 2.7 V; i(sw 100 A o(sw 0 Rev. 03 — 16 July 2009 PCA9541A Min Typ Max Unit 0.5 - + ...
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... SCL_SLAVE 4.7 [2] 4.0 4.7 4.0 4.7 4.0 [3] 0 250 - - - - [5] HIGH-to-LOW - [5] LOW-to-HIGH - - - - INT_IN input 1 INT_IN input 0.5 10 SDA clear 500 [6][7] 0 typical R and the 15 pF load capacitance. on Rev. 03 — 16 July 2009 PCA9541A 2 Fast-mode I C-bus Unit Max Min Max 0.3 - 0.3 ns 100 0 400 kHz 150 50 150 kHz - ...
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... MSB (A6) (A7 LOW HIGH 1 /f SCL SU;DAT HD;DAT and Rev. 03 — 16 July 2009 PCA9541A t t HD;STA SU;STA SU;STO Sr STOP bit 0 acknowledge condition (R/W) (A) ( VD;DAT VD;ACK SU;STO 002aab175 © NXP B.V. 2009. All rights reserved. ...
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... REC;STA V I PULSE GENERATOR Definitions test circuit Load resistance Load capacitance including jig and probe capacitance Termination resistance should be equal to the output impedance Z T Rev. 03 — 16 July 2009 PCA9541A ACK or read cycle t rst w(rst)L t rst 50 % 002aae735 6.0 V open V SS ...
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... 0.49 0.25 10.0 4.0 1.27 0.36 0.19 9.8 3.8 0.019 0.0100 0.39 0.16 0.244 0.05 0.014 0.0075 0.38 0.15 0.228 REFERENCES JEDEC JEITA MS-012 Rev. 03 — 16 July 2009 PCA9541A detail 6.2 1.0 0.7 1.05 0.25 0.25 5.8 0.4 0.6 0.039 0.028 0.041 0.01 0.01 0.016 ...
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... C-bus master selector with interrupt logic and reset 2.5 scale (1) ( 0.30 0.2 5.1 4.5 0.65 0.19 0.1 4.9 4.3 REFERENCES JEDEC JEITA MO-153 Rev. 03 — 16 July 2009 PCA9541A detail 6.6 0.75 0.4 1 0.2 0.13 6.2 0.50 0.3 EUROPEAN ...
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... 2.5 scale (1) ( 4.1 2.25 4.1 2.25 0.65 1.95 3.9 1.95 3.9 1.95 REFERENCES JEDEC JEITA MO-220 - - - Rev. 03 — 16 July 2009 PCA9541A detail 0.75 1.95 0.1 0.05 0.05 0.1 0.50 EUROPEAN PROJECTION SOT629 ISSUE DATE 01-08-08 02-10-22 © NXP B.V. 2009. All rights reserved. ...
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... Solder bath specifications, including temperature and impurities PCA9541A_3 Product data sheet 2 2-to-1 I C-bus master selector with interrupt logic and reset Rev. 03 — 16 July 2009 PCA9541A © NXP B.V. 2009. All rights reserved ...
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... Lead-free process (from J-STD-020C) Package reflow temperature ( C) 3 Volume (mm ) < 350 260 260 250 Figure 30. Rev. 03 — 16 July 2009 PCA9541A Figure 30) than a SnPb process, thus 350 220 220 350 to 2000 > 2000 260 260 250 245 245 245 © NXP B.V. 2009. All rights reserved. ...
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... Electrically Erasable Programmable Read-Only Memory ElectroStatic Discharge Field Replaceable Unit Human Body Model Inter Integrated Circuit bus Integrated Circuit Machine Model Power-On Reset Resistor-Capacitor network System Management Bus Rev. 03 — 16 July 2009 PCA9541A peak temperature time 001aac844 © NXP B.V. 2009. All rights reserved ...
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... Change notice Product data sheet - rd description”: deleted (old) 3 paragraph. characteristics”: merged Table 16 “Static characteristics” 5.5 V). DD Product data sheet - Objective data sheet - Rev. 03 — 16 July 2009 PCA9541A Supersedes PCA9541A_2 ( PCA9541A_1 - © NXP B.V. 2009. All rights reserved ...
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... Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners C-bus — logo is a trademark of NXP B.V. http://www.nxp.com salesaddresses@nxp.com Rev. 03 — 16 July 2009 PCA9541A © NXP B.V. 2009. All rights reserved ...
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... For sales office addresses, please send an email to: salesaddresses@nxp.com PCA9541A Soldering of SMD packages . . . . . . . . . . . . . . 36 Introduction to soldering Wave and reflow soldering . . . . . . . . . . . . . . . 36 Wave soldering Reflow soldering Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 38 Revision history . . . . . . . . . . . . . . . . . . . . . . . 39 Legal information . . . . . . . . . . . . . . . . . . . . . . 40 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 40 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Disclaimers Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Contact information . . . . . . . . . . . . . . . . . . . . 40 Contents Date of release: 16 July 2009 Document identifier: PCA9541A_3 All rights reserved. ...