ptn3392 NXP Semiconductors, ptn3392 Datasheet
ptn3392
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ptn3392 Summary of contents
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... The PTN3392 supports I and bridges the VESA DDC channel to the DisplayPort Interface. The PTN3392 is designed for single supply and minimizes application costs. It can be powered directly from the DisplayPort source side 3.3 V supply without a need for additional core voltage regulator. The VGA output is powered down when there is no valid DisplayPort source data being transmitted ...
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... DisplayPort configuration is able to support. PTN3392 Product data sheet (Ref. 3) for all supported video output modes 1 (Ref. 4) All information provided in this document is subject to legal disclaimers. Rev. 2 — 15 July 2010 PTN3392 2-lane DisplayPort to VGA adapter including e.g.: © NXP B.V. 2010. All rights reserved ...
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... Ordering information Type number Topside mark [1] PTN3392BS PTN3392BS [2] PTN3392BS/FX PTN3392BS [1] PTN3392BS uses latest firmware version. [2] PTN3392BS/FX uses specific firmware version (‘X’ etc., and changes according to firmware version). 5. Functional diagram PTN3392 RX PHY ANALOG SUBSYSTEM DIFF CDR, lane 0 RCV S2P V bias ...
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... All information provided in this document is subject to legal disclaimers. Rev. 2 — 15 July 2010 PTN3392 2-lane DisplayPort to VGA adapter VDDD 31 VDDD 30 LDOCAP_CORE 29 GNDD 28 GNDD 27 ...
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... All information provided in this document is subject to legal disclaimers. Rev. 2 — 15 July 2010 PTN3392 2-lane DisplayPort to VGA adapter IC Description DisplayPort main lane signal lane 0, positive DisplayPort main lane signal lane 0, negative DisplayPort main lane signal lane 1, positive DisplayPort main lane signal lane 1, negative ...
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... All information provided in this document is subject to legal disclaimers. Rev. 2 — 15 July 2010 PTN3392 2-lane DisplayPort to VGA adapter IC Description Open (internal pull-down) = logic 0: Implement VGA-side monitor detect according to VESA DisplayPort Standard v1.1a sections 7 and 8 (Ref. 1). Refer to Section 7.4.1 for behavior. ...
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... VGA to WUXGA (see Table 4 “Display resolution and pixel clock PTN3392 supports one or two DisplayPort v1.1a Main Link lanes operating at either in 2.7 Gbit/s or 1.62 Gbit/s per lane. The PTN3392 can drive up to 100 feet of analog video cable. The DisplayPort receiver comprises the following functional blocks: • ...
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... DPCD to configure and initialize the link. The DPCD is DisplayPort v1.1a compliant the responsibility of the host to only issue commands within the capability of the PTN3392 as defined in the ‘Receiver Capability Field’ in order to prevent undefined behavior. PTN3392 specific DPCD registers are listed in 7.3.1 PTN3392 specific DPCD register settings Table 3 ...
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... Byte fields that are not explicitly listed are by definition reserved (‘RES’) and their default value is 0h. PTN3392 Product data sheet PTN3392 specific DPCD registers Description [1] Not supported. BRANCH_IEEE_OUI 7:0 Branch vendor 24-bit IEEE OUI. NXP OUI = 00 BRANCH_IEEE_OUI 15:8 ...
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... The PTN3392 uses the slowest speed enabled by the mask and the PTN3392 speed capabilities. • If the result of the mask with the speed capabilities is 0000 0000b, then the PTN3392 keeps the S2 setting I change). Some specific examples are listed below for clarification purposes: • ...
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... NXP Semiconductors The PTN3392 implements two different ways to handle the HPD signal. The HPD behavior is governed by the S0 pin’s value after the reset and initialization sequence is completed (see • tied LOW, HPD is driven HIGH irrespective of whether a VGA monitor is detected. • ...
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... The PTN3392 does not cache or modify the EDID to match the capabilities of the DisplayPort link data. If the DisplayPort source drives display modes that are not specified in the EDID mode list, the PTN3392 will not detect such conditions, and will display at its output what it is presented by the DisplayPort source. Fig 4. ...
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... For proper behavior, a capacitor should be connected from the RESET_N pin to ground to slow down the internal reset pulse; 1 μF capacitance is recommended. Before link is established, the PTN3392 holds VSYNC and HSYNC signals HIGH and blanks the RGB signals. While the PTN3392 performs initialization, • ...
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... V DD(3V3) VDDA RED_N 37 24 LDOCAP_AUX GND_DAC 38 23 AUX_P RSET 39 22 AUX_N GRN 40 21 GNDA GRN_N 41 20 RRX BLU_N 42 19 PTN3392 ML0_P VDD_DAC 43 18 ML0_N VDD_DAC 44 17 GNDA_DP BLU 45 16 ML1_P HSYNC 46 15 ML1_N VSYNC 47 14 GNDA_DP SDA 48 13 1.2 kΩ 0.1 μF ...
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... VGA dongle application Ω termination is used to terminate inside the dongle, and another 75 Ω termination is typically used inside the RGB monitor. The load sensing mechanism assumes this double termination. PTN3392 Product data sheet lists some example display resolutions and clock rates that PTN3392 supports. Footnote 1 on page 2.) Total frame Horizontal ...
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... SDA and SCL inputs with respect to ground DC value at ML_LANE0+, ML_LANE0−, ML_LANE1+, ML_LANE1−, AUX_CH+, AUX_CH− inputs commercial grade All information provided in this document is subject to legal disclaimers. Rev. 2 — 15 July 2010 PTN3392 2-lane DisplayPort to VGA adapter IC Min Max −0.3 +3.8 −0.3 +4.6 −0 ...
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... RX package pins lane intra-pair skew at RX package pins; for high bit rate for reduced bit rate All information provided in this document is subject to legal disclaimers. Rev. 2 — 15 July 2010 PTN3392 2-lane DisplayPort to VGA adapter IC Min Typ Max - 180 - ...
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... V DIFF_PRE DIFF Definitions of pre-emphasis and differential voltage Conditions AUX transmitting device receiving device transmitting device receiving device All information provided in this document is subject to legal disclaimers. Rev. 2 — 15 July 2010 PTN3392 2-lane DisplayPort to VGA adapter DIFF_PRE DIFF 002aaf363 ) Min Typ [1] 0.4 ...
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... All information provided in this document is subject to legal disclaimers. Rev. 2 — 15 July 2010 2-lane DisplayPort to VGA adapter IC Min Typ Min Typ 2 - −0.5 - 0.1 × 3 3 PTN3392 Max Unit - V 0.8 V 129 mA 126 mA Max Unit 5 ±1 μ 40 © NXP B.V. 2010. All rights reserved ...
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... Product data sheet Conditions DAC-to-DAC between DAC outputs Conditions − Conditions All information provided in this document is subject to legal disclaimers. Rev. 2 — 15 July 2010 PTN3392 2-lane DisplayPort to VGA adapter IC Min Typ Max - - 240 - - 4 −1 ±0.5 +1 −1 ...
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... Product data sheet Conditions RESET_N JTAG −4 mA RESET_N −2 mA JTAG All information provided in this document is subject to legal disclaimers. Rev. 2 — 15 July 2010 PTN3392 2-lane DisplayPort to VGA adapter IC Min Typ Max 0.7 × 0.3 × ...
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... All information provided in this document is subject to legal disclaimers. Rev. 2 — 15 July 2010 2-lane DisplayPort to VGA adapter detail 0.5 5.5 0.05 0.1 0.1 0.05 0.3 EUROPEAN PROJECTION PTN3392 SOT619 ISSUE DATE 01-08-08 02-10-18 © NXP B.V. 2010. All rights reserved ...
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... Solder bath specifications, including temperature and impurities PTN3392 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 15 July 2010 PTN3392 2-lane DisplayPort to VGA adapter IC © NXP B.V. 2010. All rights reserved ...
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... Package reflow temperature (°C) 3 Volume (mm ) < 350 260 260 250 Figure 9. All information provided in this document is subject to legal disclaimers. Rev. 2 — 15 July 2010 PTN3392 2-lane DisplayPort to VGA adapter IC Figure 9) than a SnPb process, thus ≥ 350 220 220 350 to 2000 > 2000 260 260 250 ...
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... High Bit Rate High-bandwidth Digital Content Protection Hot Plug Detect Inter-Integrated Circuit bus International Electrotechnical Commission All information provided in this document is subject to legal disclaimers. Rev. 2 — 15 July 2010 PTN3392 2-lane DisplayPort to VGA adapter IC peak temperature time 001aac844 © NXP B.V. 2010. All rights reserved. ...
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... Document ID Release date PTN3392 v2 20100715 • Modifications: Table 3 “PTN3392 specific DPCD registers” sub-section, DPCD register column (sequence) is corrected from “00505h, 00505h, 00506h, 00507h” to “00505h, 00506h, 00507h, 00508h” • Figure 3 “Pin S0 behavior” • Table 4 “Display resolution and pixel clock ...
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... Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. All information provided in this document is subject to legal disclaimers. Rev. 2 — 15 July 2010 PTN3392 2-lane DisplayPort to VGA adapter IC © NXP B.V. 2010. All rights reserved ...
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... Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. http://www.nxp.com salesaddresses@nxp.com All information provided in this document is subject to legal disclaimers. Rev. 2 — 15 July 2010 PTN3392 2-lane DisplayPort to VGA adapter IC © NXP B.V. 2010. All rights reserved ...
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... Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 7 Functional description . . . . . . . . . . . . . . . . . . . 7 7.1 DisplayPort Main Link . . . . . . . . . . . . . . . . . . . . 7 7.2 DisplayPort auxiliary channel . . . . . . . . . . . . . . 7 7.3 DPCD registers 7.3.1 PTN3392 specific DPCD register settings . . . . 8 2 7.3 over AUX CH registers . . . . . . . . . . . . . . . 10 2 7.3.2.1 I C-bus speed control register (read only, 0000Ch 7.3.2.2 I C-bus speed control/status register (read/write, 00109h ...