scc2681 NXP Semiconductors, scc2681 Datasheet
scc2681
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scc2681 Summary of contents
Page 1
... SCC2681 Dual asynchronous receiver/transmitter (DUART) Product data INTEGRATED CIRCUITS 2004 Apr 06 ...
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... In addition, a flow control capability is provided to disable a remote DUART transmitter when the buffer of the receiving device is full. Also provided on the SCC2681 are a multipurpose 7-bit input port and a multipurpose 8-bit output port. These can be used as general purpose I/O ports or can be assigned specific functions (such as clock inputs or status/interrupt outputs) under program control ...
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... I Crystal 1: Crystal connection or an external clock input. A crystal of a clock the appropriate frequency (nominally 3.6864 MHz) must be supplied at all times. For crystal connections see Figure 7, Clock Timing. 3 Product data SCC2681 INDEX CORNER ...
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... Pin has an internal V current. I Power Supply: +5V supply input. I Ground – Not connected. 4 Product data SCC2681 pull-up device supplying pull-up device supplying pull-up device supplying pull-up device supplying ...
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... CMOS input levels – 0.2 V and Product data SCC2681 RATING UNIT See Note 4 C –65 to +150 C –0.5 to +6.0 V – LIMITS UNIT UNIT Min Typ Max – – ...
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... If CEN is used as the ‘strobing’ input, the parameter defines the minimum HIGH times between one CEN and the next. The RDN signal must be negated for t to guarantee that any status register changes are valid. RWD 2004 Apr PARAMETER PARAMETER Product data SCC2681 LIMITS UNIT UNIT Min Typ Max 200 – – – ...
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... RECEIVE HOLDING REG (3) RECEIVE SHIFT REGISTER MRA1, 2 CRA SRA CHANNEL B (AS ABOVE) INPUT PORT CHANGE OF STATE DETECTORS (4) IPCR ACR OUTPUT PORT FUNCTION SELECT LOGIC OPCR OPR Figure 2. Block Diagram 7 Product data SCC2681 TxDA RxDA TxDB RxDB 7 IP0-IP6 8 OP0-OP7 V CC GND SD00085 ...
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... Philips Semiconductors Dual asynchronous receiver/transmitter (DUART) BLOCK DIAGRAM The SCC2681 DUART consists of the following eight major sections: data bus buffer, operation control, interrupt control, timing, communications Channels A and B, input port and output port. Refer to the block diagram. Data Bus Buffer The data bus buffer provides the interface between the external and internal data buses ...
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... TRANSMITTER OPERATION The SCC2681 is conditioned to transmit data when the transmitter is enabled through the command register. The SCC2681 indicates to the CPU that it is ready to accept a character by setting the TxRDY bit in the status register. This condition can be programmed to generate an interrupt request at OP6 or OP7 and INTRN ...
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... FIFO while the A/D bit is loaded into the status FIFO position normally used for parity error (SRA[5] or SRB[5]). Framing error, overrun error, and break detect operate normally whether or not the receive is enabled. 10 Product data SCC2681 ...
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... In general, the contents of the MR, the CSR, and the OPCR should only be changed while the receiver(s) and transmitter(s) are not enabled, and certain changes to the ACR should only be made while the C/T is stopped. Table 1. SCC2681 Register Addressing ...
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... FFULLB FFULLA 10 = TxCB(1x RxCB(1x) BIT 5 BIT 4 BIT Product data SCC2681 BIT 2 BIT 1 BIT 0 PARITY BITS PER TYPE CHARACTER 0 = Even Odd BIT 2 BIT 1 BIT 0 STOP BIT LENGTH 0.813 8 = 1.563 C = 1.813 5 = 0.875 ...
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... BIT 5 BIT 4 BIT 3 OP5 OP4 OP3 change no change no change 1 = reset bit 1 = reset bit 1 = reset bit 13 Product data SCC2681 BIT 2 BIT 1 BIT 0 DELTA DELTA DELTA IP 2 INT IP 1 INT IP 0 INT 0 = Off 0 = Off 0 = Off BIT 2 BIT 1 ...
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... A received break is echoed as received until the next valid start bit is detected. The user must exercise care when switching into and out of the various modes. The selected mode will be activated immediately upon mode selection, even if this occurs in the middle of a received 14 Product data SCC2681 ...
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... The error with 8 bits not parity and one stop bit is 4.6 stop bit length of 9/16 is used, the error tolerance will approach 0 due to a variable error 1/16 bit time in receiver clock phase alignment to the start bit. 15 Product data SCC2681 Error (%) 0 0 –0.069 0.059 ...
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... IP5–1 CRA[0] – Enable Channel A Receiver Enables operation of the Channel A receiver. If not in the special wake up mode, this also forces the receiver into the search for start-bit state. Note: Performing disable and enable at the same time results in disable. 16 Product data SCC2681 ...
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... CPU reads the RHR, if after this read there are not more characters still in the FIFO. SRB – Channel B Status Register The bit definitions for this register are identical to the bit definitions for SRA, except that all status applies to the Channel B receiver and transmitter and the corresponding inputs and outputs. 17 Product data SCC2681 ...
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... The setting of these bits can be programmed to generate an interrupt to the CPU. IPCR[3:0] – IP3, IP2, IP1, IP0 Current State These bits provide the current state of the respective inputs. The information is unlatched and reflects the state of the input pins at the time the IPCR is read. 18 Product data SCC2681 ...
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... On power up and after reset the timer/counter comes up stopped and in the timer mode. It will require a start counter command (a read at address 0xE) to start it. Because it cannot be shut off or stopped once started, and runs continuously in timer mode recommended that at initialization, the output port (OP3) should be 19 Product data SCC2681 ...
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... TxRDY sets at the end of the “start bit” time during the start bit that the data in the transmit holding register is transferred to the transmit shift register. Non-standard baud rates are available as shown in Table 5 below, via the BRG Test function. 20 Product data SCC2681 ...
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... ACR[ 110 134.5 150 300 600 1,200 2,000 2,400 4,800 1,800 9,600 19.2 k Timer I/O2 – 16 I/O2 – 16 I/O2 – 1 I/O2 – Product data SCC2681 BRG Extended Rates ACR[ 4,800 7,200 880 880 1,076 1,076 19.2 k 14.4 k 28.8 k 28.8 k 57.6 k 57.6 k 115.2 k 115.2 k 1,050 2,000 57.6 k 57.6 k 4,800 4,800 57 ...
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... RES Figure 3. Reset Timing RWD NOT VALID FLOAT VALID t RWD VALID Figure 4. Bus Timing OLD DATA 1.5V M Figure 5. Port Timing 22 Product data SCC2681 SD00086 SD00087 V OH NEW DATA V OL SD00089 ...
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... WHEN TTL DEVICE t CTC SCC2681 = 150 TYPICAL CRYSTAL SPECIFICATION 2 – 4 MHz ): 12 – PARALLEL RESONANT, FUNDAMENTAL MODE Figure 7. Clock Timing 23 Product data SCC2681 +0. SD00090 + INTERNAL CLOCK DRIVERS SD00724 ...
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... Timing shown for MR2( 2004 Apr 06 1 BIT TIME ( CLOCKS) t TXD t TCS Figure 8. Transmit t t RXS RXH SD00093 Figure 9. Receiver Timing D2 D3 BREAK D3 START D4 STOP BREAK BREAK TRANSMITTED Figure 10. Transmitter Timing 24 Product data SCC2681 SD00092 WILL D6 NOT BE OPR( SD00094 ...
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... BE LOST Figure 11. Receiver Timing BIT 9 BIT MR1( ADD#2 BIT 9 BIT ADD#1 STATUS DATA D0 Figure 12. Wake-Up Mode 25 Product data SCC2681 D6, D7, D8 WILL BE LOST STATUS DATA STATUS DATA RESET BY COMMAND SD00095 BIT 9 ADD#2 1 BIT 9 BIT 9 ADD STATUS DATA ...
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... Philips Semiconductors Dual asynchronous receiver/transmitter (DUART) DIP28: plastic dual in-line package; 28 leads (600 mil) 2004 Apr 06 26 Product data SCC2681 SOT117-1 ...
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... Philips Semiconductors Dual asynchronous receiver/transmitter (DUART) DIP40: plastic dual in-line package; 40 leads (600 mil) 2004 Apr 06 27 Product data SCC2681 SOT129-1 ...
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... Philips Semiconductors Dual asynchronous receiver/transmitter (DUART) PLCC44: plastic leaded chip carrier; 44 leads 2004 Apr 06 28 Product data SCC2681 SOT187-2 ...
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... Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Fax: + 24825 Document order number: 29 Product data SCC2681 Koninklijke Philips Electronics N.V. 2004 All rights reserved. Printed in U.S.A. Date of release: 04-04 9397 750 12075 ...