ST72F321AR9TA STMicroelectronics, ST72F321AR9TA Datasheet
ST72F321AR9TA
Specifications of ST72F321AR9TA
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ST72F321AR9TA Summary of contents
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MCU with 32 to 60K Flash/ROM, ADC, Features Memories ■ – 32K to 60K dual voltage High Density Flash (HDFlash) or ROM with read-out protection capability. In-Application Programming and In-Circuit Programming for HDFlash devices – ...
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DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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ACTIVE-HALT AND HALT MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Voltage Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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FLASH OPTION BYTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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DESCRIPTION The ST72F321 Flash and ST72321 ROM devices are members of the ST7 microcontroller family de- signed for mid-range applications. All devices are based on a common industry- standard 8-bit core, featuring an enhanced instruc- tion set and are ...
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ST72321Rx ST72321ARx ST72321Jx 2 PIN DESCRIPTION Figure 2. 64-Pin LQFP 14x14 and 10x10 Package Pinout (HS) PE4 (HS) PE5 (HS) PE6 (HS) PE7 PWM3 / PB0 PWM2 / PB1 PWM1 / PB2 PWM0 / PB3 ARTCLK / (HS) PB4 ARTIC1 ...
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Figure 3. 44-Pin LQFP Package Pinout RDI / PE1 PB0 PB1 PB2 PB3 (HS) PB4 AIN0 / PD0 AIN1 / PD1 AIN2 / PD2 AIN3 / PD3 AIN4 / PD4 ST72321Rx ST72321ARx ST72321Jx ...
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ST72321Rx ST72321ARx ST72321Jx PIN DESCRIPTION (Cont’d) For external pin connection guidelines, refer to See “ELECTRICAL CHARACTERISTICS” on page 138. Legend / Abbreviations for Table 2 Type input output supply Input level Dedicated ...
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Pin n° Pin Name DD_3 SS_3 PF0/MCO/AIN8 PF1 (HS)/BEEP PF2 (HS PF3/OCMP2_A/AIN9 I/O C PF4/OCMP1_A AIN10 30 ...
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ST72321Rx ST72321ARx ST72321Jx Pin n° Pin Name PA2 PA3 (HS DD_1 SS_1 PA4 (HS PA5 (HS PA6 ...
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ISTICS for more details. 3. OSC1 and OSC2 pins connect a crystal/ceramic resonator external source to the on-chip oscil- lator; see Section 1 DESCRIPTION more details the chip, each I/O port may have ...
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ST72321Rx ST72321ARx ST72321Jx 3 REGISTER & MEMORY MAP As shown in Figure 4, the MCU is capable of ad- dressing 64K bytes of memories and I/O registers. The available memory locations consist of 128 bytes of register locations ...
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Table 3. Hardware Register Map Register Address Block 0000h PADR 2) 0001h Port A PADDR 0002h PAOR 0003h PBDR 2) 0004h Port B PBDDR 0005h PBOR 0006h PCDR 0007h Port C PCDDR 0008h PCOR 0009h PDDR 2) 000Ah Port D ...
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ST72321Rx ST72321ARx ST72321Jx Register Address Block 002Ah WATCHDOG WDGCR 002Bh SICSR 002Ch MCCSR MCC 002Dh MCCBCR 002Eh to 0030h 0031h TACR2 0032h TACR1 0033h TACSR 0034h TAIC1HR 0035h TAIC1LR 0036h TAOC1HR 0037h TAOC1LR 0038h TIMER A TACHR 0039h TACLR 003Ah ...
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Register Address Block 0058h to 006Fh 0070h ADCCSR 0071h ADC ADCDRH 0072h ADCDRL 0073h PWMDCR3 0074h PWMDCR2 0075h PWMDCR1 0076h PWMDCR0 0077h PWMCR 0078h PWM ART ARTCSR 0079h ARTCAR 007Ah ARTARR ARTICCSR 007Bh ARTICR1 007Ch ARTICR2 007Dh 007Eh 007Fh Legend: ...
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ST72321Rx ST72321ARx ST72321Jx 4 FLASH PROGRAM MEMORY 4.1 Introduction The ST7 dual voltage High Density Flash (HDFlash non-volatile memory that can be electrically erased as a single block or by individu- al sectors and programmed on a Byte-by-Byte ...
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FLASH PROGRAM MEMORY (Cont’d) 4.4 ICC Interface ICC needs a minimum of 4 and pins to be connected to the programming tool (see These pins are: – RESET: device reset – device power supply ground ...
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... Flash memory programming can be fully custom- ized (number of bytes to program, program loca- tions, or selection serial communication interface for downloading). When using an STMicroelectronics or third-party programming tool that supports ICP and the spe- cific microcontroller device, the user needs only to implement the ICP hardware interface on the ap- ...
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CENTRAL PROCESSING UNIT 5.1 INTRODUCTION This CPU has a full 8-bit architecture and contains six internal registers allowing efficient 8-bit data manipulation. 5.2 MAIN FEATURES Enable executing 63 basic instructions ■ Fast 8-bit by 8-bit multiply ■ 17 main ...
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ST72321Rx ST72321ARx ST72321Jx CENTRAL PROCESSING UNIT (Cont’d) Condition Code Register (CC) Read/Write Reset Value: 111x1xxx The 8-bit Condition Code register contains the in- terrupt masks and four flags representative of the result of the ...
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CENTRAL PROCESSING UNIT (Cont’d) Stack Pointer (SP) Read/Write Reset Value: 01 FFh SP7 SP6 SP5 SP4 SP3 The Stack Pointer is a 16-bit register which is al- ways pointing to the next free ...
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ST72321Rx ST72321ARx ST72321Jx 6 SUPPLY, RESET AND CLOCK MANAGEMENT The device includes a range of utility features for securing the application in critical situations (for example in case of a power brown-out), and re- ducing the number of external components. ...
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MULTI-OSCILLATOR (MO) The main clock of the ST7 can be generated by three different source types coming from the multi- oscillator block: an external source ■ 4 crystal or ceramic resonator oscillators ■ an internal high frequency RC oscillator ...
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ST72321Rx ST72321ARx ST72321Jx 6.3 RESET SEQUENCE MANAGER (RSM) 6.3.1 Introduction The reset sequence manager includes three RE- SET sources as shown in Figure External RESET source pulse ■ Internal LVD RESET (Low Voltage Detection) ■ Internal WATCHDOG RESET ■ These ...
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RESET SEQUENCE MANAGER (Cont’d) The RESET pin is an asynchronous signal which plays a major role in EMS performance noisy environment recommended to follow the guidelines mentioned in the electrical characteris- tics section. If the external ...
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ST72321Rx ST72321ARx ST72321Jx 6.4 SYSTEM INTEGRITY MANAGEMENT (SI) The System Integrity Management block contains the Low Voltage Detector (LVD), age Detector (AVD) functions managed by the SICSR register. 6.4.1 Low Voltage Detector (LVD) The Low Voltage Detector function ...
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SYSTEM INTEGRITY MANAGEMENT (Cont’d) 6.4.2 Auxiliary Voltage Detector (AVD) The Voltage Detector function (AVD) is based on an analog comparison between reference value and the V IT+(AVD) ply or the external EVD pin voltage level (V The ...
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ST72321Rx ST72321ARx ST72321Jx SYSTEM INTEGRITY MANAGEMENT (Cont’d) 6.4.2.2 Monitoring a Voltage on the EVD pin This mode is selected by setting the AVDS bit in the SICSR register. The AVD circuitry can generate an interrupt when the AVDIE bit of ...
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SYSTEM INTEGRITY MANAGEMENT (Cont’d) 6.4.4 Register Description SYSTEM INTEGRITY (SI) CONTROL/STATUS REGISTER (SICSR) Read/Write Reset Value: 000x 000x (00h) 7 AVD AVD AVD LVD Bit 7 = AVDS Voltage Detection selection This bit is set ...
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ST72321Rx ST72321ARx ST72321Jx 7 INTERRUPTS 7.1 INTRODUCTION The ST7 enhanced interrupt management pro- vides the following features: Hardware interrupts ■ Software interrupt (TRAP) ■ Nested or concurrent interrupt management ■ with flexible interrupt management: – software programmable ...
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INTERRUPTS (Cont’d) Servicing Pending Interrupts As several interrupts can be pending at the same time, the interrupt to be taken into account is deter- mined by the following two-step process: – the highest software priority interrupt is serviced, – if ...
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ST72321Rx ST72321ARx ST72321Jx INTERRUPTS (Cont’d) 7.3 INTERRUPTS AND LOW POWER MODES All interrupts allow the processor to exit the WAIT low power mode. On the contrary, only external and other specified interrupts allow the processor to exit from the HALT ...
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INTERRUPTS (Cont’d) 7.5 INTERRUPT REGISTER DESCRIPTION CPU CC REGISTER INTERRUPT BITS Read/Write Reset Value: 111x 1010 (xAh Bit I1, I0 Software Interrupt Priority These two bits indicate the current interrupt soft- ...
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ST72321Rx ST72321ARx ST72321Jx INTERRUPTS (Cont’d) Table 7. Dedicated Interrupt Instruction Set Instruction New Description HALT Entering Halt mode IRET Interrupt routine return JRM Jump if I1:0=11 (level 3) JRNM Jump if I1:0<>11 POP CC Pop CC from the Stack RIM ...
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INTERRUPTS (Cont’d) Table 8. Interrupt Mapping Source N° Block RESET Reset TRAP Software interrupt 0 TLI External top level interrupt 1 MCC/RTC Main clock controller time base interrupt 2 ei0 External interrupt port A3..0 3 ei1 External interrupt port F2..0 ...
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ST72321Rx ST72321ARx ST72321Jx INTERRUPTS (Cont’d) Figure 22. External Interrupt Control bits PORT A [3:0] INTERRUPTS PAOR.3 PADDR.3 PA3 IPA BIT PORT F [2:0] INTERRUPTS PFOR.2 PFDDR.2 PF2 PORT B [3:0] INTERRUPTS PBOR.3 PBDDR.3 PB3 IPB BIT PORT B [7:4] INTERRUPTS ...
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EXTERNAL INTERRUPT CONTROL REGISTER (EICR) Read/Write Reset Value: 0000 0000 (00h) 7 IS11 IS10 IPB IS21 IS20 Bit 7:6 = IS1[1:0] ei2 and ei3 sensitivity The interrupt sensitivity, defined using the IS1[1:0] bits, is applied to the following external ...
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ST72321Rx ST72321ARx ST72321Jx INTERRUPTS (Cont’d) Table 9. Nested Interrupts Register Map and Reset Values Address Register 7 (Hex.) Label 0024h I1_3 ISPR0 1 Reset Value 0025h I1_7 ISPR1 1 Reset Value 0026h ISPR2 I1_11 1 Reset Value 0027h ISPR3 Reset ...
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POWER SAVING MODES 8.1 INTRODUCTION To give a large measure of flexibility to the applica- tion in terms of power consumption, four main power saving modes are implemented in the ST7 (see Figure 23): SLOW, WAIT (SLOW WAIT), AC- ...
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ST72321Rx ST72321ARx ST72321Jx POWER SAVING MODES (Cont’d) 8.3 WAIT MODE WAIT mode places the MCU in a low power con- sumption mode by stopping the CPU. This power saving mode is selected by calling the ‘WFI’ instruction. All peripherals remain ...
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POWER SAVING MODES (Cont’d) 8.4 ACTIVE-HALT AND HALT MODES ACTIVE-HALT and HALT modes are the two low- est power consumption modes of the MCU. They are both entered by executing the ‘HALT’ instruc- tion. The decision to enter either in ...
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ST72321Rx ST72321ARx ST72321Jx POWER SAVING MODES (Cont’d) 8.4.2 HALT MODE The HALT mode is the lowest power consumption mode of the MCU entered by executing the ‘HALT’ instruction when the OIE bit of the Main Clock Controller Status ...
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POWER SAVING MODES (Cont’d) 8.4.2.1 Halt Mode Recommendations – Make sure that an external event is available to wake up the microcontroller from Halt mode. – When using an external interrupt to wake up the microcontroller, reinitialize the corresponding I/O ...
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ST72321Rx ST72321ARx ST72321Jx 9 I/O PORTS 9.1 INTRODUCTION The I/O ports offer different functional modes: – transfer of data through digital inputs and outputs and for specific pins: – external interrupt generation – alternate signal input/output for the on-chip pe- ...
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I/O PORTS (Cont’d) Figure 30. I/O Port General Block Diagram ALTERNATE REGISTER OUTPUT ACCESS ALTERNATE ENABLE DR DDR OR If implemented OR SEL DDR SEL DR SEL 1 0 EXTERNAL INTERRUPT SOURCE ( Table 10. I/O Port Mode ...
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ST72321Rx ST72321ARx ST72321Jx I/O PORTS (Cont’d) Table 11. I/O Port Configurations NOT IMPLEMENTED IN V TRUE OPEN DRAIN I/O PORTS PAD NOT IMPLEMENTED IN TRUE OPEN DRAIN V I/O PORTS PAD NOT IMPLEMENTED IN TRUE OPEN DRAIN V I/O PORTS ...
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I/O PORTS (Cont’d) CAUTION: The alternate function must not be ac- tivated as long as the pin is configured as input with interrupt, in order to avoid generating spurious interrupts. Analog alternate function When the pin is used as an ...
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ST72321Rx ST72321ARx ST72321Jx I/O PORTS (Cont’d) 9.5.1 I/O Port Implementation The I/O port register configurations are summa- rised as follows. Standard Ports PA5:4, PC7:0, PD7:0, PE7:3, PE1:0, PF7:3, MODE floating input pull-up input open drain output push-pull output Interrupt Ports ...
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I/O PORTS (Cont’d) Table 13. I/O Port Register Map and Reset Values Address Register 7 (Hex.) Label Reset Value 0 of all I/O port registers 0000h PADR 0001h PADDR MSB 0002h PAOR 0003h PBDR 0004h PBDDR MSB 0005h PBOR 0006h ...
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ST72321Rx ST72321ARx ST72321Jx 10 ON-CHIP PERIPHERALS 10.1 WATCHDOG TIMER (WDG) 10.1.1 Introduction The Watchdog timer is used to detect the occur- rence of a software fault, usually generated by ex- ternal interference or by unforeseen logical condi- tions, which causes ...
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WATCHDOG TIMER (Cont’d) 10.1.4 How to Program the Watchdog Timeout Figure 2 shows the linear relationship between the 6-bit value to be loaded in the Watchdog Counter (CNT) and the resulting timeout duration in milli- seconds. This can be used ...
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ST72321Rx ST72321ARx ST72321Jx WATCHDOG TIMER (Cont’d) Figure 34. Exact Timeout Duration (t WHERE (LSB + 128 min0 OSC2 t = 16384 x t max0 OSC2 t = 125ns MHz OSC2 OSC2 ...
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WATCHDOG TIMER (Cont’d) 10.1.5 Low Power Modes Mode Description SLOW No effect on Watchdog. WAIT No effect on Watchdog. OIE bit in WDGHALT bit MCCSR in Option register Byte 0 HALT 0 1 10.1.6 Hardware Watchdog Option If Hardware Watchdog ...
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ST72321Rx ST72321ARx ST72321Jx Table 14. Watchdog Timer Register Map and Reset Values Address Register 7 (Hex.) Label WDGCR WDGA 002Ah Reset Value 0 56/193 ...
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MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK AND BEEPER (MCC/RTC) The Main Clock Controller consists of three differ- ent functions: a programmable CPU clock prescaler ■ a clock-out signal to supply external devices ■ a real time clock timer ...
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ST72321Rx ST72321ARx ST72321Jx MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK (Cont’d) 10.2.5 Low Power Modes Mode Description No effect on MCC/RTC peripheral. WAIT MCC/RTC interrupt cause the device to exit from WAIT mode. No effect on MCC/RTC counter (OIE bit ...
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MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK (Cont’d) Bit 0 = OIF Oscillator interrupt flag This bit is set by hardware and cleared by software reading the MCCSR register. It indicates when set that the main oscillator has reached the ...
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ST72321Rx ST72321ARx ST72321Jx 10.3 PWM AUTO-RELOAD TIMER (ART) 10.3.1 Introduction The Pulse Width Modulated Auto-Reload Timer on-chip peripheral consists of an 8-bit auto reload counter with compare/capture capabilities and of a 7-bit prescaler clock source. These resources allow five possible ...
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ON-CHIP PERIPHERALS (Cont’d) 10.3.2 Functional Description Counter The free running 8-bit counter is fed by the output of the prescaler, and is incremented on every ris- ing edge of the clock signal possible to read or write the ...
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ST72321Rx ST72321ARx ST72321Jx ON-CHIP PERIPHERALS (Cont’d) Independent PWM signal generation This mode allows up to four Pulse Width Modulat- ed signals to be generated on the PWMx output pins with minimum core processing overhead. This function is stopped during HALT ...
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ON-CHIP PERIPHERALS (Cont’d) Output compare and Time base interrupt On overflow, the OVF flag of the ARTCSR register is set and an overflow interrupt request is generat the overflow interrupt enable bit, OIE, in the ARTCSR register, is ...
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ST72321Rx ST72321ARx ST72321Jx ON-CHIP PERIPHERALS (Cont’d) Input capture function This mode allows the measurement of external signal pulse widths through ARTICRx registers. Each input capture can generate an interrupt inde- pendently on a selected input signal transition. This event is ...
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ON-CHIP PERIPHERALS (Cont’d) 10.3.3 Register Description CONTROL / STATUS REGISTER (ARTCSR) Read/Write Reset Value: 0000 0000 (00h) 7 EXCL CC2 CC1 CC0 TCE Bit 7 = EXCL External Clock This bit is set and cleared by software. It selects the ...
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ST72321Rx ST72321ARx ST72321Jx ON-CHIP PERIPHERALS (Cont’d) PWM CONTROL REGISTER (PWMCR) Read/Write Reset Value: 0000 0000 (00h) 7 OE3 OE2 OE1 OE0 OP3 Bit 7:4 = OE[3:0] PWM Output Enable These bits are set and cleared by software. They enable or ...
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ON-CHIP PERIPHERALS (Cont’d) INPUT CAPTURE CONTROL / STATUS REGISTER (ARTICCSR) Read/Write Reset Value: 0000 0000 (00h CS2 CS1 CIE2 Bit 7:6 = Reserved, always read as 0. Bit 5:4 = CS[2:1] Capture Sensitivity These bits are set ...
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ST72321Rx ST72321ARx ST72321Jx PWM AUTO-RELOAD TIMER (Cont’d) Table 16. PWM Auto-Reload Timer Register Map and Reset Values Address Register 7 Label (Hex.) PWMDCR3 DC7 0073h 0 Reset Value PWMDCR2 DC7 0074h 0 Reset Value PWMDCR1 DC7 0075h 0 Reset Value ...
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TIMER 10.4.1 Introduction The timer consists of a 16-bit free-running counter driven by a programmable prescaler. It may be used for a variety of purposes, including pulse length measurement two input sig- nals (input capture) ...
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ST72321Rx ST72321ARx ST72321Jx 16-BIT TIMER (Cont’d) Figure 42. Timer Block Diagram f CPU 8 high EXEDG 1/2 COUNTER 1/4 REGISTER 1/8 ALTERNATE EXTCLK pin COUNTER REGISTER CC[1:0] OVERFLOW DETECT CIRCUIT ICF1 OCF1 TOF ICF2 (Control/Status Register) ICIE OCIE TOIE FOLV2 ...
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TIMER (Cont’d) 16-bit read sequence: (from either the Counter Register or the Alternate Counter Register). Beginning of the sequence Read MS Byte At t0 Other instructions Returns the buffered Read At t0 +Δt LS Byte value ...
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ST72321Rx ST72321ARx ST72321Jx 16-BIT TIMER (Cont’d) Figure 43. Counter Timing Diagram, Internal Clock Divided by 2 CPU CLOCK INTERNAL RESET TIMER CLOCK COUNTER REGISTER TIMER OVERFLOW FLAG (TOF) Figure 44. Counter Timing Diagram, Internal Clock Divided by 4 CPU CLOCK ...
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TIMER (Cont’d) 10.4.3.3 Input Capture In this section, the index, i, may because there are two input capture functions in the 16-bit timer. The two 16-bit input capture registers (IC1R and IC2R) are used to ...
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ST72321Rx ST72321ARx ST72321Jx 16-BIT TIMER (Cont’d) Figure 46. Input Capture Block Diagram ICAP1 pin EDGE DETECT CIRCUIT2 ICAP2 pin IC2R Register 16-BIT 16-BIT FREE RUNNING COUNTER Figure 47. Input Capture Timing Diagram TIMER CLOCK COUNTER REGISTER ICAPi PIN ICAPi FLAG ...
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TIMER (Cont’d) 10.4.3.4 Output Compare In this section, the index, i, may because there are two output compare functions in the 16- bit timer. This function can be used to control an output waveform or ...
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ST72321Rx ST72321ARx ST72321Jx 16-BIT TIMER (Cont’d) Notes: 1. After a processor write cycle to the OCiHR reg- ister, the output compare function is inhibited until the OCiLR register is also written the OCiE bit is not set, the ...
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TIMER (Cont’d) Figure 49. Output Compare Timing Diagram, f INTERNAL CPU CLOCK COUNTER REGISTER OUTPUT COMPARE REGISTER i (OCRi) OUTPUT COMPARE FLAG i (OCFi) OCMPi PIN (OLVLi = 1) Figure 50. Output Compare Timing Diagram, f INTERNAL CPU CLOCK ...
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ST72321Rx ST72321ARx ST72321Jx 16-BIT TIMER (Cont’d) 10.4.3.5 One Pulse Mode One Pulse mode enables the generation of a pulse when an external event occurs. This mode is selected via the OPM bit in the CR2 register. The One Pulse mode ...
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TIMER (Cont’d) Figure 51. One Pulse Mode Timing Example IC1R 01F8 COUNTER ICAP1 OCMP1 Note: IEDG1 = 1, OC1R = 2ED0h, OLVL1 = 0, OLVL2 = 1 Figure 52. Pulse Width Modulation Mode Timing Example with 2 Output Compare ...
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ST72321Rx ST72321ARx ST72321Jx 16-BIT TIMER (Cont’d) 10.4.3.6 Pulse Width Modulation Mode Pulse Width Modulation (PWM) mode enables the generation of a signal with a frequency and pulse length determined by the value of the OC1R and OC2R registers. Pulse Width ...
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TIMER (Cont’d) 10.4.4 Low Power Modes Mode No effect on 16-bit Timer. WAIT Timer interrupts cause the device to exit from WAIT mode. 16-bit Timer registers are frozen. In HALT mode, the counter stops counting until Halt mode is ...
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ST72321Rx ST72321ARx ST72321Jx 16-BIT TIMER (Cont’d) 10.4.7 Register Description Each Timer is associated with three control and status registers, and with six pairs of data registers (16-bit values) relating to the two input captures, the two output compares, the counter ...
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TIMER (Cont’d) CONTROL REGISTER 2 (CR2) Read/Write Reset Value: 0000 0000 (00h) 7 OC1E OC2E OPM PWM CC1 CC0 IEDG2 EXEDG Bit 7 = OC1E Output Compare 1 Pin Enable. This bit is used only to output the signal ...
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ST72321Rx ST72321ARx ST72321Jx 16-BIT TIMER (Cont’d) CONTROL/STATUS REGISTER (CSR) Read/Write (bits 7:3 read only) Reset Value: xxxx x0xx (xxh) 7 ICF1 OCF1 TOF ICF2 OCF2 TIMD Bit 7 = ICF1 Input Capture Flag input capture (reset value). ...
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TIMER (Cont’d) INPUT CAPTURE 1 HIGH REGISTER (IC1HR) Read Only Reset Value: Undefined This is an 8-bit read only register that contains the high part of the counter value (transferred by the input capture 1 event). 7 MSB INPUT ...
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ST72321Rx ST72321ARx ST72321Jx 16-BIT TIMER (Cont’d) OUTPUT COMPARE 2 (OC2HR) Read/Write Reset Value: 1000 0000 (80h) This is an 8-bit register that contains the high part of the value to be compared to the CHR register. 7 MSB OUTPUT COMPARE ...
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TIMER (Cont’d) Table 18. 16-Bit Timer Register Map and Reset Values Address Register 7 (Hex.) Label Timer A: 32 CR1 ICIE Timer B: 42 Reset Value Timer A: 31 CR2 OC1E Timer B: 41 Reset Value Timer A: 33 ...
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ST72321Rx ST72321ARx ST72321Jx 10.5 SERIAL PERIPHERAL INTERFACE (SPI) 10.5.1 Introduction The Serial Peripheral Interface (SPI) allows full- duplex, synchronous, serial communication with external devices. An SPI system may consist of a master and one or more slaves however the SPI ...
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SERIAL PERIPHERAL INTERFACE (Cont’d) – SS: Slave select: This input signal acts as a ‘chip select’ to let the SPI master communicate with slaves indi- vidually and to avoid contention on the data lines. Slave SS inputs can be driven ...
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ST72321Rx ST72321ARx ST72321Jx SERIAL PERIPHERAL INTERFACE (Cont’d) 10.5.3.2 Slave Select Management As an alternative to using the SS pin to control the Slave Select signal, the application can choose to manage the Slave Select signal by software. This is configured ...
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SERIAL PERIPHERAL INTERFACE (Cont’d) 10.5.3.3 Master Mode Operation In master mode, the serial clock is output on the SCK pin. The clock frequency, polarity and phase are configured by software (refer to the description of the SPICSR register). Note: The ...
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ST72321Rx ST72321ARx ST72321Jx SERIAL PERIPHERAL INTERFACE (Cont’d) 10.5.4 Clock Phase and Clock Polarity Four possible timing relationships may be chosen by software, using the CPOL and CPHA bits (See Figure 57). Note: The idle state of SCK must correspond to ...
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SERIAL PERIPHERAL INTERFACE (Cont’d) 10.5.5 Error Flags 10.5.5.1 Master Mode Fault (MODF) Master mode fault occurs when the master device has its SS pin pulled low. When a Master mode fault occurs: – The MODF bit is set and an ...
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ST72321Rx ST72321ARx ST72321Jx SERIAL PERIPHERAL INTERFACE (Cont’d) 10.5.5.4 Single Master Systems A typical single master system may be configured, using an MCU as the master and four MCUs as slaves (see Figure 59). The master device selects the individual slave ...
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SERIAL PERIPHERAL INTERFACE (Cont’d) 10.5.6 Low Power Modes Mode Description No effect on SPI. WAIT SPI interrupt events cause the device to exit from WAIT mode. SPI registers are frozen. In HALT mode, the SPI is inactive. SPI oper- ation ...
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ST72321Rx ST72321ARx ST72321Jx SERIAL PERIPHERAL INTERFACE (Cont’d) 10.5.8 Register Description CONTROL REGISTER (SPICR) Read/Write Reset Value: 0000 xxxx (0xh) 7 SPIE SPE SPR2 MSTR CPOL Bit 7 = SPIE Serial Peripheral Interrupt Enable. This bit is set and cleared by ...
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SERIAL PERIPHERAL INTERFACE (Cont’d) CONTROL/STATUS REGISTER (SPICSR) Read/Write (some bits Read Only) Reset Value: 0000 0000 (00h) 7 SPIF WCOL OVR MODF Bit 7 = SPIF Serial Peripheral Data Transfer Flag (Read only). This bit is set by hardware when ...
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ST72321Rx ST72321ARx ST72321Jx SERIAL PERIPHERAL INTERFACE (Cont’d) Table 20. SPI Register Map and Reset Values Address Register 7 (Hex.) Label SPIDR MSB 0021h Reset Value SPICR SPIE 0022h Reset Value SPICSR SPIF 0023h Reset Value 98/193 ...
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SERIAL COMMUNICATIONS INTERFACE (SCI) 10.6.1 Introduction The Serial Communications Interface (SCI) offers a flexible means of full-duplex data exchange with external equipment requiring an industry standard NRZ asynchronous serial data format. The SCI of- fers a very wide range ...
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ST72321Rx ST72321ARx ST72321Jx SERIAL COMMUNICATIONS INTERFACE (Cont’d) Figure 60. SCI Block Diagram Write Transmit Data Register (TDR) TDO Transmit Shift Register RDI TRANSMIT CONTROL CR2 TIE TCIE RIE SCI INTERRUPT CONTROL TRANSMITTER CLOCK f CPU 100/193 Read Received Data Register ...
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SERIAL COMMUNICATIONS INTERFACE (Cont’d) 10.6.4 Functional Description The block diagram of the Serial Control Interface, is shown in Figure 1. It contains six dedicated reg- isters: – Two control registers (SCICR1 & SCICR2) – A status register (SCISR) – A ...
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ST72321Rx ST72321ARx ST72321Jx SERIAL COMMUNICATIONS INTERFACE (Cont’d) 10.6.4.2 Transmitter The transmitter can send data words of either bits depending on the M bit status. When the M bit is set, word length is 9 bits and the ...
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SERIAL COMMUNICATIONS INTERFACE (Cont’d) 10.6.4.3 Receiver The SCI can receive data words of either bits. When the M bit is set, word length is 9 bits and the MSB is stored in the R8 bit in the ...
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ST72321Rx ST72321ARx ST72321Jx SERIAL COMMUNICATIONS INTERFACE (Cont’d) Figure 62. SCI Baud Rate and Extended Prescaler Block Diagram EXTENDED PRESCALER TRANSMITTER RATE CONTROL EXTENDED TRANSMITTER PRESCALER REGISTER EXTENDED RECEIVER PRESCALER REGISTER EXTENDED PRESCALER RECEIVER RATE CONTROL f CPU /PR /16 SCP1 ...
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SERIAL COMMUNICATIONS INTERFACE (Cont’d) Framing Error A framing error is detected when: – The stop bit is not recognized on reception at the expected time, following either a de-synchroni- zation or excessive noise. – A break is received. When the ...
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ST72321Rx ST72321ARx ST72321Jx SERIAL COMMUNICATIONS INTERFACE (Cont’d) 10.6.4.7 Parity Control Parity control (generation of parity bit in transmis- sion and parity checking in reception) can be ena- bled by setting the PCE bit in the SCICR1 register. Depending on the ...
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SERIAL COMMUNICATIONS INTERFACE (Cont’d) 10.6.4.9 Clock Deviation Causes The causes which contribute to the total deviation are: – Deviation due to transmitter error (Local TRA oscillator error of the transmitter or the trans- mitter is transmitting at a ...
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ST72321Rx ST72321ARx ST72321Jx SERIAL COMMUNICATIONS INTERFACE (Cont’d) 10.6.5 Low Power Modes Mode Description No effect on SCI. WAIT SCI interrupts cause the device to exit from Wait mode. SCI registers are frozen. HALT In Halt mode, the SCI stops transmitting/re- ...
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SERIAL COMMUNICATIONS INTERFACE (Cont’d) 10.6.7 Register Description STATUS REGISTER (SCISR) Read Only Reset Value: 1100 0000 (C0h) 7 TDRE TC RDRF IDLE OR Bit 7 = TDRE Transmit data register empty. This bit is set by hardware when the content ...
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ST72321Rx ST72321ARx ST72321Jx SERIAL COMMUNICATIONS INTERFACE (Cont’d) CONTROL REGISTER 1 (SCICR1) Read/Write Reset Value: x000 0000 (x0h SCID M WAKE Bit Receive data bit 8. This bit is used to store the 9th bit ...
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SERIAL COMMUNICATIONS INTERFACE (Cont’d) CONTROL REGISTER 2 (SCICR2) Read/Write Reset Value: 0000 0000 (00h) 7 TIE TCIE RIE ILIE TE Bit 7 = TIE Transmitter interrupt enable. This bit is set and cleared by software. 0: Interrupt is inhibited 1: ...
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ST72321Rx ST72321ARx ST72321Jx SERIAL COMMUNICATIONS INTERFACE (Cont’d) DATA REGISTER (SCIDR) Read/Write Reset Value: Undefined Contains the Received or Transmitted data char- acter, depending on whether it is read from or writ- ten to. 7 DR7 DR6 DR5 DR4 DR3 The ...
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SERIAL COMMUNICATIONS INTERFACE (Cont’d) EXTENDED RECEIVE PRESCALER DIVISION REGISTER (SCIERPR) Read/Write Reset Value: 0000 0000 (00h) Allows setting of the Extended Prescaler rate divi- sion factor for the receive circuit. 7 ERPR ERPR ERPR ERPR ERPR ...
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ST72321Rx ST72321ARx ST72321Jx SERIAL COMMUNICATION INTERFACE (Cont’d) Table 23. SCI Register Map and Reset Values Address Register 7 (Hex.) Label SCISR TDRE 0050h Reset Value 1 SCIDR MSB 0051h Reset Value x SCIBRR SCP1 0052h Reset Value 0 SCICR1 R8 ...
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I C BUS INTERFACE (I2C) 10.7.1 Introduction 2 The I C Bus Interface serves as an interface be- tween the microcontroller and the serial I provides both multimaster and slave functions, 2 and controls all I C bus-specific ...
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ST72321Rx ST72321ARx ST72321Jx BUS INTERFACE (Cont’d) Acknowledge may be enabled and disabled by software. 2 The I C interface address and/or general call ad- dress can be selected by software. 2 The speed of the I C ...
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I C BUS INTERFACE (Cont’d) 10.7.4 Functional Description Refer to the CR, SR1 and SR2 registers in 10.7.7. for the bit definitions default the I C interface operates in Slave mode (M/SL bit is cleared) except when ...
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ST72321Rx ST72321ARx ST72321Jx INTERFACE (Cont’d) How to release the SDA / SCL lines Set and subsequently clear the STOP bit while BTF is set. The SDA/SCL lines are released after the transfer of the current byte. SMBus ...
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I C BUS INTERFACE (Cont’d) Master Transmitter Following the address transmission and after SR1 register has been read, the master sends bytes from the DR register to the SDA line via the inter- nal shift register. The master waits ...
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ST72321Rx ST72321ARx ST72321Jx BUS INTERFACE (Cont’d) Figure 66. Transfer Sequencing 7-bit Slave receiver: S Address A Data1 EV1 7-bit Slave transmitter: S Address A Data1 EV1 EV3 7-bit Master receiver: S Address A EV5 EV6 7-bit Master ...
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I C BUS INTERFACE (Cont’d) 10.7.5 Low Power Modes Mode 2 No effect interface. WAIT interrupts cause the device to exit from WAIT mode registers are frozen. 2 HALT In ...
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ST72321Rx ST72321ARx ST72321Jx BUS INTERFACE (Cont’d) 10.7.7 Register Description CONTROL REGISTER (CR) Read / Write Reset Value: 0000 0000 (00h ENGC START ACK Bit 7:6 = Reserved. Forced to 0 ...
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I C BUS INTERFACE (Cont’ STATUS REGISTER 1 (SR1) Read Only Reset Value: 0000 0000 (00h) 7 EVF ADD10 TRA BUSY BTF Bit 7 = EVF Event flag. This bit is set by hardware as soon ...
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ST72321Rx ST72321ARx ST72321Jx BUS INTERFACE (Cont’d) Bit 1 = M/SL Master/Slave. This bit is set by hardware as soon as the interface is in Master mode (writing START=1 cleared by hardware after detecting a Stop ...
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I C BUS INTERFACE (Cont’ CLOCK CONTROL REGISTER (CCR) Read / Write Reset Value: 0000 0000 (00h) 7 FM/SM CC6 CC5 CC4 CC3 Bit 7 = FM/SM Fast/Standard I This bit is set and cleared by ...
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ST72321Rx ST72321ARx ST72321Jx BUS INTERFACE (Cont’ OWN ADDRESS REGISTER (OAR1) Read / Write Reset Value: 0000 0000 (00h) 7 ADD7 ADD6 ADD5 ADD4 ADD3 ADD2 ADD1 ADD0 7-bit Addressing Mode Bit 7:1 = ADD[7:1] ...
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I²C BUS INTERFACE (Cont’d) 2 Table 24 Register Map and Reset Values Address Register 7 Label (Hex.) I2CCR 0018h Reset Value 0 I2CSR1 EVF 0019h Reset Value 0 I2CSR2 001Ah Reset Value 0 I2CCCR FM/SM 001Bh Reset Value ...
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ST72321Rx ST72321ARx ST72321Jx 10.8 10-BIT A/D CONVERTER (ADC) 10.8.1 Introduction The on-chip Analog to Digital Converter (ADC) pe- ripheral is a 10-bit, successive approximation con- verter with internal sample and hold circuitry. This peripheral has multiplexed analog ...
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A/D CONVERTER (ADC) (Cont’d) 10.8.3 Functional Description The conversion is monotonic, meaning that the re- sult never decreases if the analog input does not and never increases if the analog input does not. If the input voltage (V ) ...
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ST72321Rx ST72321ARx ST72321Jx 10-BIT A/D CONVERTER (ADC) (Cont’d) 10.8.6 Register Description CONTROL/STATUS REGISTER (ADCCSR) Read/Write (Except bit 7 read only) Reset Value: 0000 0000 (00h) 7 EOC SPEED ADON 0 CH3 Bit 7 = EOC End of Conversion This bit ...
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A/D CONVERTER (Cont’d) Table 25. ADC Register Map and Reset Values Address Register 7 (Hex.) Label ADCCSR EOC 0070h Reset Value 0 ADCDRH D9 0071h Reset Value 0 ADCDRL 0072h Reset Value 0 ST72321Rx ST72321ARx ST72321Jx ...
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ST72321Rx ST72321ARx ST72321Jx 11 INSTRUCTION SET 11.1 CPU ADDRESSING MODES The CPU features 17 different addressing modes which can be classified in seven main groups: Addressing Mode Example Inherent nop Immediate ld A,#$55 Direct ld A,$55 Indexed ld A,($55,X) Indirect ...
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INSTRUCTION SET OVERVIEW (Cont’d) 11.1.1 Inherent All Inherent instructions consist of a single byte. The opcode fully specifies all the required informa- tion for the CPU to process the operation. Inherent Instruction NOP No operation TRAP S/W Interrupt Wait For ...
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ST72321Rx ST72321ARx ST72321Jx INSTRUCTION SET OVERVIEW (Cont’d) 11.1.6 Indirect Indexed (Short, Long) This is a combination of indirect and short indexed addressing modes. The operand is referenced by its memory address, which is defined by the un- signed addition of ...
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INSTRUCTION SET OVERVIEW (Cont’d) 11.2 INSTRUCTION GROUPS The ST7 family devices use an Instruction Set consisting of 63 instructions. The instructions may Load and Transfer Stack operation Increment/Decrement Compare and Tests Logical operations Bit Operation Conditional Bit Test and Branch ...
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ST72321Rx ST72321ARx ST72321Jx INSTRUCTION SET OVERVIEW (Cont’d) Mnemo Description ADC Add with Carry ADD Addition AND Logical And BCP Bit compare A, Memory BRES Bit Reset BSET Bit Set BTJF Jump if bit is false (0) BTJT Jump if bit ...
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INSTRUCTION SET OVERVIEW (Cont’d) Mnemo Description JRULE Jump Load MUL Multiply NEG Negate (2's compl) NOP No Operation OR OR operation POP Pop from the Stack PUSH Push onto the Stack RCF Reset ...
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ST72321Rx ST72321ARx ST72321Jx 12 ELECTRICAL CHARACTERISTICS 12.1 PARAMETER CONDITIONS Unless otherwise specified, all voltages are re- ferred 12.1.1 Minimum and Maximum values Unless otherwise specified the minimum and max- imum values are guaranteed in the worst ...
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ABSOLUTE MAXIMUM RATINGS Stresses above those listed as “absolute maxi- mum ratings” may cause permanent damage to the device. This is a stress rating only and func- tional operation of the device under these condi- 12.2.1 Voltage Characteristics Symbol ...
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ST72321Rx ST72321ARx ST72321Jx 12.2.3 Thermal Characteristics Symbol T Storage temperature range STG T Maximum junction temperature (see J 12.3 OPERATING CONDITIONS 12.3.1 General Operating Conditions Symbol Parameter f Internal clock frequency CPU Standard voltage range (except Flash Write/Erase ...
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OPERATING CONDITIONS (Cont’d) 12.3.2 Operating Conditions with Low Voltage Detector (LVD) Subject to general operating conditions for V Symbol Parameter Reset release threshold V IT+(LVD) (V rise) DD Reset generation threshold V IT-(LVD) (V fall LVD voltage threshold ...
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ST72321Rx ST72321ARx ST72321Jx 12.4 SUPPLY CURRENT CHARACTERISTICS The following current consumption specified for the ST7 functional operating modes over temperature range does not take into account the clock source current consumption. To get the total device consump- tion, the two ...
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SUPPLY CURRENT CHARACTERISTICS (Cont’d) 12.4.1.1 Power Consumption vs f Figure 72. Typical I in RUN mode DD 8MHz 9 4MHz 8 2MHz 1MHz 3.2 3.6 4 4.4 Vdd (V) Figure 73. Typical ...
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ST72321Rx ST72321ARx ST72321Jx SUPPLY CURRENT CHARACTERISTICS (Cont’d) 12.4.2 Supply and Clock Managers The previous current consumption specified for the ST7 functional operating modes over temperature range does not take into account the clock source current consumption. To get the total ...
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SUPPLY CURRENT CHARACTERISTICS (Cont’d) 12.4.3 On-Chip Peripherals Measured on LQFP64 generic board T Symbol Parameter I 16-bit Timer supply current DD(TIM) I ART PWM supply current DD(ART SPI supply current DD(SPI SCI supply current DD(SCI) 5) ...
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ST72321Rx ST72321ARx ST72321Jx 12.5 CLOCK AND TIMING CHARACTERISTICS Subject to general operating conditions for V 12.5.1 General Timings Symbol Parameter t Instruction cycle time c(INST) Interrupt reaction time t = Δt v(IT v(IT) c(INST) 12.5.2 External Clock ...
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CLOCK AND TIMING CHARACTERISTICS (Cont’d) 12.5.3 Crystal and Ceramic Resonator Oscillators The ST7 internal clock can be supplied with four different Crystal/Ceramic resonator oscillators. All the information given in this paragraph is based on characterization results with specified typical ex- ...
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ST72321Rx ST72321ARx ST72321Jx Figure 77. Typical Application with a Crystal or Ceramic Resonator . Figure 78 Application with a Crystal or Ceramic Resonator for ROM (LQFP64 or any 48/60K ROM) WHEN RESONATOR WITH INTEGRATED CAPACITORS ...
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CLOCK AND TIMING CHARACTERISTICS (Cont’d) f OSC Supplier (MHz Notes: 1. Resonator characteristics given by the ceramic resonator manufacturer. 2. SMD = [-R0: Plastic tape package ( LEAD = [-A0: Flat pack package (Radial taping Ho= ...
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ST72321Rx ST72321ARx ST72321Jx CLOCK CHARACTERISTICS (Cont’d) 12.5.4 RC Oscillators Symbol Parameter Internal RC oscillator frequency f OSC (RCINT) See Figure 79 Figure 79. Typical f OSC(RCINT) 4 3.8 3.6 3.4 3 (°C) A 150/193 Conditions ...
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CLOCK CHARACTERISTICS (Cont’d) Note: 1. Data based on characterization results. 12.5.5 PLL Characteristics Symbol Parameter f PLL input frequency range OSC Instantaneous PLL jitter Δ CPU CPU Note: 1. Data characterized but not tested. The user must ...
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ST72321Rx ST72321ARx ST72321Jx 12.6 MEMORY CHARACTERISTICS 12.6.1 RAM and Hardware Registers Symbol Parameter V Data retention mode RM 12.6.2 FLASH Memory DUAL VOLTAGE HDFLASH MEMORY Symbol Parameter f Operating frequency CPU V Programming voltage Supply current DD ...
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EMC CHARACTERISTICS Susceptibility tests are performed on a sample ba- sis during product characterization. 12.7.1 Functional EMS (Electro Magnetic Susceptibility) Based on a simple running application on the product (toggling 2 LEDs through I/O ports), the product is stressed ...
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ST72321Rx ST72321ARx ST72321Jx EMC CHARACTERISTICS (Cont’d) 12.7.2 Electro Magnetic Interference (EMI) Based on a simple application running on the product (toggling 2 LEDs through the I/O ports), the product is monitored in terms of emission. This emission test is in ...
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EMC CHARACTERISTICS (Cont’d) 12.7.3 Absolute Maximum Ratings (Electrical Sensitivity) Based on two different tests (ESD and LU) using specific measurement methods, the product is stressed in order to determine its performance in terms of electrical sensitivity. For more details, re- ...
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ST72321Rx ST72321ARx ST72321Jx 12.8 I/O PORT PIN CHARACTERISTICS 12.8.1 General Characteristics Subject to general operating conditions for V Symbol Parameter V Input low level voltage IL V Input high level voltage IH V Schmitt trigger voltage hysteresis hys Injected Current ...
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I/O PORT PIN CHARACTERISTICS (Cont’d) 12.8.2 Output Driving Current Subject to general operating conditions for V Symbol Parameter Output low level voltage for a standard I/O pin when 8 pins are sunk at same time (see Figure 83 ...
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ST72321Rx ST72321ARx ST72321Jx I/O PORT PIN CHARACTERISTICS (Cont’d) Figure 86. Typical V vs 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0 2.5 3 3.5 Vdd(V ) Figure 87. Typical V vs ...
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CONTROL PIN CHARACTERISTICS 12.9.1 Asynchronous RESET Pin Subject to general operating conditions for V Symbol Parameter V Input low level voltage IL V Input high level voltage IH V Schmitt trigger voltage hysteresis hys V Output low level voltage ...
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ST72321Rx ST72321ARx ST72321Jx CONTROL PIN CHARACTERISTICS (Cont’d) Figure 89. RESET pin protection when LVD is enabled. Required EXTERNAL RESET 0.01μF Figure 90. RESET pin protection when LVD is disabled. USER EXTERNAL RESET CIRCUIT 0.01μF Required Note 1: – The reset ...
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CONTROL PIN CHARACTERISTICS (Cont’d) 12.9.2 ICCSEL/V Pin PP Subject to general operating conditions for V Symbol Parameter V Input low level voltage IL V Input high level voltage IH I Input leakage current L Figure 91. Two typical Applications with ...
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ST72321Rx ST72321ARx ST72321Jx 12.10 TIMER PERIPHERAL CHARACTERISTICS Subject to general operating conditions for V Refer to I/O port characteristics for more details on the input/output alternate function characteristics (out- put compare, input capture, external clock, PWM output...). 12.10.1 8-Bit PWM-ART ...
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COMMUNICATION INTERFACE CHARACTERISTICS 12.11.1 SPI - Serial Peripheral Interface Subject to general operating conditions for and T unless otherwise specified. CPU A Symbol Parameter f SCK SPI clock frequency 1/t c(SCK) t r(SCK) SPI clock rise ...
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ST72321Rx ST72321ARx ST72321Jx COMMUNICATION INTERFACE CHARACTERISTICS (Cont’d) Figure 93. SPI Slave Timing Diagram with CPHA=1 SS INPUT t su(SS) CPHA=1 CPOL=0 CPHA=1 CPOL=1 t w(SCKH) t a(SO) t w(SCKL) see MISO OUTPUT HZ note 2 t su(SI) MOSI INPUT Figure ...
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COMMUNICATION INTERFACE CHARACTERISTICS (Cont’d) 2 12.11 Inter IC Control Interface Subject to general operating conditions for V , and T unless otherwise specified CPU Symbol Parameter t SCL clock low time w(SCLL) t SCL clock ...
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ST72321Rx ST72321ARx ST72321Jx COMMUNICATION INTERFACE CHARACTERISTICS (Cont’d) The following table gives the values to be written in the I2CCCR register to obtain the required I SCL line frequency. Table 28. SCL Frequency Table f SCL V = 4.1 V (kHz) ...
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ADC CHARACTERISTICS Subject to general operating conditions for V Symbol Parameter f ADC clock frequency ADC V Analog reference voltage AREF V Conversion voltage range AIN R External input impedance AIN C External capacitor on analog input AIN ...
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ST72321Rx ST72321ARx ST72321Jx ADC CHARACTERISTICS (Cont’d) Figure 96. R max AIN ADC (pF) PARASITIC Figure 98. Typical A/D Converter Application R AIN V AIN Notes: ...
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ADC CHARACTERISTICS (Cont’d) 12.12.1 Analog Power Supply and Reference Pins Depending on the MCU pin count, the package may feature separate V AREF power supply pins. These pins supply power to the A/D converter cell and function as the high ...
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ST72321Rx ST72321ARx ST72321Jx 10-BIT ADC CHARACTERISTICS (Cont’d) 12.12.3 ADC Accuracy 1) Conditions: V =5V DD Symbol Parameter Total unadjusted error Offset error Gain Error Differential linearity ...
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PACKAGE CHARACTERISTICS 13.1 PACKAGE MECHANICAL DATA Figure 101. 64-Pin Low Profile Quad Flat Package (14x14 Figure 102. 64-Pin Low Profile Quad Flat Package (10 x10 ST72321Rx ST72321ARx ST72321Jx A Dim ...
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ST72321Rx ST72321ARx ST72321Jx PACKAGE MECHANICAL DATA (Cont’d) Figure 103. 44-Pin Low Profile Quad Flat Package D D1 Figure 104. 32-Pin Low Profile Quad Flat Package - D D1 172/193 ...
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THERMAL CHARACTERISTICS Symbol Package thermal resistance (junction to ambient) R thJA P Power dissipation D T Maximum junction temperature Jmax Notes: 1. The maximum chip-junction temperature is based on technology characteristics. 2. The maximum power dissipation is obtained from ...
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ST72321Rx ST72321ARx ST72321Jx 13.3 SOLDERING AND GLUEABILITY INFORMATION Refer to JEDEC specification JSTD020D for a de- scription of the recommended reflow oven profile for these packages. In order to meet environmental requirements, ST offers this device in different grades of ...
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ST72321 DEVICE CONFIGURATION AND ORDERING INFORMATION Each device is available for production in user pro- grammable versions (FLASH) as well as in factory coded versions (ROM/FASTROM). ST72321 devices are ROM versions. ST72P321 devices are Factory Advanced Service Technique ROM ...
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ST72321Rx ST72321ARx ST72321Jx ST72321 DEVICE CONFIGURATION AND ORDERING INFORMATION (Cont’d) OPT0= FMP_R Flash memory read-out protection Read-out protection, when selected, provides a protection against Program Memory content ex- traction and against write access to Flash memo- ry. Erasing the option ...
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... OPTION LIST appended. ST72321Rx ST72321ARx ST72321Jx Refer to application note AN1635 for information on the counter listing returned by ST after code has been transferred. The STMicroelectronics Sales Organization will be pleased to provide de- tailed information on contractual points. Caution: The Readout Protection binary value is inverted between ROM and FLASH products. The option byte checksum will differ between ROM and FLASH ...
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ST72321Rx ST72321ARx ST72321Jx Figure 105. Ordering information scheme Example: Family ST7 microcontroller family Memory type F: Flash Blank : ROM P = FASTROM Sub-family 325 No. of pins (LQFP64 10x10 package) R ...
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... ST723251 DEVICE CONFIGURATION AND ORDERING INFORMATION (Cont’d) Figure 106. ROM Factory Coded Device Types DEVICE PACKAGE VERSION ST72321Rx ST72321ARx ST72321Jx / XXX Code name (defined by STMicroelectronics Standard -40 to +125 °C 6= Standard -40 to +85 °C T= Plastic Thin Quad Flat Pack ST72321AR9, ST72321AR7, ST72321AR6, ST72321R9, ST72321R7, ST72321R6 ...
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... Phone No Reference/ROM Code *The ROM code name is assigned by STMicroelectronics. ROM code must be sent in .S19 format. .Hex extension cannot be processed. Device Type/Memory Size/Package (check only one option): ...
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... DEVICE CONFIGURATION AND ORDERING INFORMATION (Cont’d) 14.3 DEVELOPMENT TOOLS Development tools for the ST7 microcontrollers in- clude a complete range of hardware systems and software tools from STMicroelectronics and third- party tool suppliers. The range of tools includes solutions to help you evaluate microcontroller pe- ripherals, develop and debug your application, and program your microcontrollers ...
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ST72321Rx ST72321ARx ST72321Jx DEVICE CONFIGURATION AND ORDERING INFORMATION (Cont’d) Table 30. Suggested List of Socket Types Device LQFP64 14 x14 LQFP64 10 x10 LQFP44 10 X10 14.3.4 Socket and Emulator Information For information on the type of socket that is ...
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ST7 APPLICATION NOTES Table 31. ST7 Application Notes IDENTIFICATION DESCRIPTION APPLICATION EXAMPLES AN1658 SERIAL NUMBERING IMPLEMENTATION AN1720 MANAGING THE READ-OUT PROTECTION IN FLASH MICROCONTROLLERS AN1755 A HIGH RESOLUTION/PRECISION THERMOMETER USING ST7 AND NE555 AN1756 CHOOSING A DALI IMPLEMENTATION STRATEGY ...
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ST72321Rx ST72321ARx ST72321Jx Table 31. ST7 Application Notes IDENTIFICATION DESCRIPTION AN1947 ST7MC PMAC SINE WAVE MOTOR CONTROL SOFTWARE LIBRARY GENERAL PURPOSE AN1476 LOW COST POWER SUPPLY FOR HOME APPLIANCES AN1526 ST7FLITE0 QUICK REFERENCE NOTE AN1709 EMC DESIGN FOR ST MICROCONTROLLERS ...
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Table 31. ST7 Application Notes IDENTIFICATION DESCRIPTION AN1071 HALF DUPLEX USB-TO-SERIAL BRIDGE USING THE ST72611 USB MICROCONTROLLER AN1106 TRANSLATING ASSEMBLY CODE FROM HC05 TO ST7 PROGRAMMING ST7 FLASH MICROCONTROLLERS IN REMOTE ISP MODE (IN-SITU PRO- AN1179 GRAMMING) AN1446 USING THE ...
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ST72321Rx ST72321ARx ST72321Jx 15 KNOWN LIMITATIONS 15.1 ALL FLASH AND ROM DEVICES 15.1.1 External RC option The External RC clock source option described in previous datasheet revisions is no longer support- ed and has been removed from this specification. 15.1.2 ...
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TNZ Y jrne OUT LD A,sema ; check the semaphore status if edge is detected CP A,#01 jrne OUT call call_routine; call the interrupt routine OUT:LD A,#00 LD sema,A .call_routine ; entry to call_routine PUSH A PUSH X PUSH CC ...
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The interrupt flag is cleared within any interrupt routine with higher or identical priority level – The interrupt flag is cleared in any part of the code while this interrupt is disabled If these conditions are not met, the ...
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KNOWN LIMITATIONS (Cont’d) 15.1.7 SCI Wrong Break duration Description A single break character is sent by setting and re- setting the SBK bit in the SCICR2 register. In some cases, the break character may have a long- er duration than ...
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To identify these parts, check the internal sales type on the box label or the trace code marking on the package. Rev Internal Salestype Trace Code 72F321xxx$A2 Rev Q 72F321xxx$U2 72F321xxx$A8 Rev S 72F321xxx$U8 72F321xxx$A3 Rev 9 (full spec) 72F321xxx$U3 ...
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LVD Startup behaviour When the LVD is enabled, the MCU reaches its authorized operating voltage from a reset state. However, in some devices, the reset state is re- leased when VDD is approximately between 0.8V and 1.5V ...
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REVISION HISTORY Table 32. Revision History Date Revision Added “related documentation” section in specific chapters throughout document Flash readout protection sentence added Chapter updated, Vt POR max modified in Added Modified description of t Added Note ...
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... Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. ...