ucb1400 NXP Semiconductors, ucb1400 Datasheet
ucb1400
Available stocks
Related parts for ucb1400
ucb1400 Summary of contents
Page 1
... Rev. 02 — 21 June 2002 1. General description The UCB1400 is a stereo audio codec equipped with touch screen and power management interfaces. It integrates an AC ’97 Rev. 2.1 interface for communication link host controller such as the Intel Xscale™ processor. The stereo audio codec inputs connect directly to a microphone or line level sources such player ...
Page 2
... MUX I/F VOLTAGE 10-BIT ADC REFERENCE AC LINK I/O AND CONTROL OSC 2-CHANNEL 20-BIT AUDIO DAC DIGITAL 2-CHANNEL I/O 20-BIT AUDIO ADC Rev. 02 — 21 June 2002 UCB1400 and power management monitor Version 7 1.4 mm SOT313-2 SDATA_IN SDATA_OUT BIT_CLK RESET SYNC IRQOUT LINE_OUT_L, LINE_OUT_R LINE_IN_L, LINE_IN_R, MICP ...
Page 3
... MHz crystal / master clock input 24.576 MHz crystal AC-link master reset AC-link sample sync AC-link 12.288 MHz serial data clock AC-link serial data output. UCB1400 input stream AC-link serial data input. UCB1400 output stream Interrupt output © Koninklijke Philips Electronics N.V. 2002. All rights reserved ...
Page 4
... I/O Hi-Z Rev. 02 — 21 June 2002 UCB1400 and power management monitor Description Microphone input Microphone ground switch input Line in left channel Line in right channel Line out left channel Line out right channel Analog voltage input Touch screen positive X-plate ...
Page 5
... INTERRUPT STATUS/CLEAR (0x62) ADC READY MUX (0x64, 0x66) ADC ADC DATA CONTROL (0x66) DATA (0x68) Rev. 02 — 21 June 2002 UCB1400 Audio codec with touch screen controller and power management monitor DSP (0x6A) SHAPER LOOP BACK (0x20) DECIMATION FILTER OVFL AC97 / AUDIO ...
Page 6
... Register reset: which only initializes the UCB1400 registers to their default states. Initiated by a write to register 0x00. After signaling a reset to UCB1400, the AC ’97 Controller should not attempt to play or capture audio data until it has sampled a “Codec Ready” indication from UCB1400. 9397 750 09611 ...
Page 7
... Digital interface 8.3.1 AC-link digital serial interface protocol The UCB1400 incorporates a 5-pin digital serial interface that links it to the AC ’97 Controller. AC-link is a bi-directional, fixed rate, serial PCM digital stream. It handles multiple input, and output audio and modem streams, as well as control register accesses employing a time division multiplexed (TDM) scheme ...
Page 8
... BIT_CLK, the AC ’97 Controller transitions SDATA_OUT into the first bit position of slot 0 (Valid Frame bit). Each new bit position is presented to AC-link on a rising edge of BIT_CLK, and subsequently sampled by UCB1400 on the following falling edge of BIT_CLK. This sequence ensures that data transitions, and subsequent sample points for both incoming and outgoing data streams are time aligned ...
Page 9
... Note that shadowing of the control register file on the AC ’97 Controller is an option left open to the implementation of the AC ’97 Controller. UCB1400’s control register file is readable as well as writable to provide more robust testability. Audio output frame slot 1 communicates control register address, and write/read command information to the UCB1400 ...
Page 10
... Slot 0: TAG: flags whether UCB1400 is in the ‘Codec Ready’ state or not. If the ‘Codec Ready’ bit this indicates that UCB1400 is not ready for normal operation. This condition is normal following the deassertion of power-on reset, for example, while UCB1400’s voltage references settle. When the AC-link ‘ ...
Page 11
... Fig 9. Start of an audio input frame. SDATA_IN’s composite stream is MSB justified (MSB first) with all non-valid bit positions (for assigned and/or unassigned time slots) stuffed with 0s by the UCB1400. SDATA_IN data is sampled on the falling edges of BIT_CLK. 9397 750 09611 Product data 20 ...
Page 12
... Slot 12: GPIO status: input data. UCB1400 does not make use of slot 12 to report its IO pin status. It only uses the GPIO_INT as an optional means (when the GIEN bit is set in the Feature CSR1 register) to signify an interrupt event (in addition to pin IRQOUT). ...
Page 13
... UCB1400. 8.3.4 AC-link low power mode The AC-link signals can be placed in a low power mode. When the UCB1400’s PR4 bit is set to ‘1’ in the Power-down status and control register (0x26), both BIT_CLK and SDATA_IN will be brought to, and held at, a logic LOW voltage level. ...
Page 14
... BIT_CLK, SYNC is treated as an asynchronous input used in the generation of a warm reset to the UCB1400. The UCB1400 must not respond with the activation of BIT_CLK until SYNC has been sampled LOW again by the UCB1400. This will preclude the false detection of a new audio frame. 8.4 Accessing the UCB1400 The UCB1400 supports only primary codec confi ...
Page 15
... Philips Semiconductors In order for the AC ’97 Digital Controller to access the UCB1400, the 2-bit Codec ID field (chip select) (LSBs of Output Slot 0) must be set to ‘0’ (see UCB1400 shall monitor the Frame Valid, Slot 1 Valid Command Address, Slot 2 Valid Command Data and Codec ID bits, and respond only if properly accessed by the AC ’ ...
Page 16
... Controller in the next audio output frame. An active output slot is defined as any slot supported by UCB1400 that is not in a power-down state. In case of UCB1400, the only SLOTREQ bits used are that for slot 3 and slot 4 request (bits 11 and 10 of input slot 1). SLOTREQ bits for all other slots shall be stuffed with 0s by UCB1400 ...
Page 17
... Regardless of the test mode, the AC ’97 Controller must issue a cold reset to resume normal operation of the UCB1400. 8.7.1 ATE in-circuit test mode When the UCB1400 is placed in the ATE test mode, its digital AC-link outputs (i.e., BIT_CLK and SDATA_IN) shall be driven to a high impedance state. This allows ATE in-circuit testing of the AC ’97 Controller. ...
Page 18
... Philips Semiconductors 8.8 General purpose IOs Fig 12. Block diagram of IO pin circuitry. The UCB1400 has 10 programmable digital input/output (I/O) pins. These pins can be independently programmed as input or output using the IOD[9:0] bits in the IO Direction Register (0x5C). The output data is determined by the content of the IO[9:0] bits in the IO Data Register (0x5A), while the actual status of these pins can be read from the same register bits ...
Page 19
... GPIO_INT bit of input slot 12 when BIT_CLK is on. • Rising SDATA_IN when BIT_CLK is off. 9397 750 09611 Product data Audio codec with touch screen controller and power management monitor Rev. 02 — 21 June 2002 UCB1400 © Koninklijke Philips Electronics N.V. 2002. All rights reserved ...
Page 20
... Fig 14. Audio codec block diagram. 9.1 ADC analog front-end The analog front-end of the UCB1400 consists of one stereo ADC with a selector in front of it. Using this selector, one can either select the microphone input with a dedicated Low Noise Amplifier (LNA), or the line input with a Programmable Gain Amplifi ...
Page 21
... The filter characteristics are shown in Table Table 6: Item Pass-band ripple Stop band Dynamic range 9397 750 09611 Product data ) or to the MICGND pin of the UCB1400. The latter will decrease the SS UCB1400 AV DD MICP MICGND AV SS SN00226 ‘ ...
Page 22
... In that case, the OVFL bit in the Feature Control/Status Register 1 (0x6A) is set. In addition, an interrupt is generated on the IRQOUT pin of the UCB1400 whenever the OVLP bit or the OVLN bit is set in the Positive and/or Negative INT Enable Registers. ...
Page 23
... CLPR or CLPG) in the Extra Interrupt register (0x70). In addition, an interrupt is generated on the IRQOUT pin of UCB1400 whenever the CLPP or CLPN bit is set in the Positive and/or Negative INT Enable Registers. In that case, the CPLS bit will be set in the INT Clear/Status register (index 0x62) ...
Page 24
... PR0 bit in the Power-down Control/Status register (0x26) is set. The output path is disabled when the PR1 bit of the same register is set. This provides the user the means to reduce the current consumption of UCB1400 if one part of the audio codec is not used in the application. When both the input and output paths are disabled, the PR3 bit of the same register can also be set to turn off the audio reference to further reduce power consumption ...
Page 25
... PXP, MXP, PYP, MYP and PXG, MYG, PYG, MYG bits in the touch screen control register. Possible conflicting settings (grounding and powering of a touch screen pin at the same time) are detected by the UCB1400. In that case, the UCB1400 will ground the touch screen pin. ...
Page 26
... TM[1:0] in the touch screen control register according to Table 8: TM[1: 10.2 Operational modes The UCB1400 supports three modes of touch screen measurements: position, pressure, and plate resistances. Additionally, an interrupt mode is provided for detection of touch events. 10.2.1 Position measurement VBIAS TOUCH TSPX R X2 ...
Page 27
... The current flowing through the touch screen is a direct indication for the resistance between both plates. A compensation for the series resistance, formed by the touch screen plates and the internal 1 k resistance of the UCB1400 will improve the accuracy of this measurement. 9397 750 09611 ...
Page 28
... int int R X2 TSPX TSMY t TSPY R Y2 Rev. 02 — 21 June 2002 UCB1400 Audio codec with touch screen controller and power management monitor VBIAS TSPX TSPY TSMX TO ADC 1 k SN00249 SCHMITT TRIGGER TSPX TSPY TSMX SCHMITT TRIGGER SN00250 © Koninklijke Philips Electronics N.V. 2002. All rights reserved. ...
Page 29
... Y plate has to be grounded. In this case, the touch screen is not biased by the active touch screen bias circuit, but by a resistor to AV biases the touch screen and the UCB1400 does not consume power unless the touch screen is touched. The voltage on the X plate terminals drops if the screen is pressed ...
Page 30
... ADC conversion has to be started; and finally, the ADC result has to be read from the ADC Data register (0x68). The UCB1400 has two different modes to start the ADC conversion, which are selected by the ASE bit in the ADC Control register (0x66). When ASE is ‘0’, the ADC conversion is started directly by writing a ‘ ...
Page 31
... ADC Data register (0x68). Fig 23. AD0-AD3 resistive dividers block diagram. The applied voltage on the four analog inputs of the UCB1400 (AD0-AD3) is attenuated before it is applied to the ADC input multiplexer using on-chip resistive dividers. These high voltage inputs are optimized to handle voltages larger than the used supply voltage. The built-in resistive voltage dividers are only activated if the corresponding analog input is selected. The resistive dividers are made fl ...
Page 32
... Philips Semiconductors 12. Register definition The following tables describe the register definition for the UCB1400. The UCB1400 shall follow the AC ’97 2.1 Interoperability Requirements and Recommendations as follows: • Non-implemented or reserved register bits: All reserved or non-implemented register bits (marked ‘X’ in the tables) are required to return ‘0’ when read. ...
Page 33
Table 10: Register definitions Shaded registers are read-only. Reg Name D15 D14 D13 (HEX) 00 Reset Master Volume MM X ML5 04-0C Reserved MIC ...
Page 34
Table 10: Register definitions …continued Shaded registers are read-only. Reg Name D15 D14 D13 (HEX) 60 Negative INT OVLN CLPN TMXN TPXN ADCN X enable 62 INT clear/status OVLS CLPS TMXS 64 ...
Page 35
... X R Reserved. ML5 - ML0 RW Left channel attenuation in 1.5 dB step (000000 = 0 dB; 111111 = 94.5 dB Reserved. MR5 - MR0 RW Right channel attenuation in 1.5 dB step (000000 = 0 dB; 111111 = 94.5 dB). Rev. 02 — 21 June 2002 UCB1400 and power management monitor D11 D10 ID9 ...
Page 36
... This mode is primarily intended when the mono MIC input is selected at the left channel (SL = 000). Rev. 02 — 21 June 2002 UCB1400 and power management monitor D11 D10 D9 D8 ...
Page 37
... X Description of General Purpose register bits Symbol Type Description X R Reserved. LPBK RW ADC/DAC loopback mode (ADC output to DAC input Reserved. Rev. 02 — 21 June 2002 UCB1400 and power management monitor D11 D10 D9 D8 GL3 GL2 GL1 GL0 GR3 GR2 GR1 ...
Page 38
... AC-link will have no effect on read-only bits When the ‘Codec Ready’ indicator bit (SDATA_IN slot 0, bit 15 indicates that the UCB1400 control and status registers are in a fully operational state. The AC ’97 Controller must further probe this Power-down Control/Status register to determine exactly which subsections, if any, are ready ...
Page 39
... Description of Extended Audio ID register bits Symbol Type Description ID1 - ID0 R Always ‘0’ (UCB1400 is a primary codec Reserved. VRA R Always ‘1’ (Variable Rate PCM Audio supported). Extended Audio Status and Control register D15 D14 D13 D12 ...
Page 40
... In VRA mode (VRA = 1 in register 0x2A), if the value written to the register is supported, that value will be echoed back when read, otherwise the closest (higher in case of a tie) sample rate supported is returned. The UCB1400’s DAC and ADC are capable of operating at independent rates. ...
Page 41
... Description X R Reserved. IOD9 - IOD0 bit is ‘1’, the associated IO pin is defined as output bit is ‘0’, the associated IO pin is defined as input. Rev. 02 — 21 June 2002 UCB1400 and power management monitor D11 D10 IO9 IO8 D3 D2 ...
Page 42
... RW If ‘1’, the falling edge interrupt of ADC Ready is enabled Reserved. ION9 - ION0 bit is ‘1’, the falling edge interrupt of the associated IO pin is enabled. Rev. 02 — 21 June 2002 UCB1400 and power management monitor D11 D10 D9 D8 ADCP X IOP9 IOP8 ...
Page 43
... BIAS RW If ‘1’, the touch screen bias circuitry is activated. If ‘0’, the touch screen bias is disabled to minimize power consumption. Rev. 02 — 21 June 2002 UCB1400 and power management monitor D11 D10 D9 D8 ADCS X IOS9 ...
Page 44
... Must be set to ‘0’ (other values reserved for testing purposes only). AI2 - AI0 RW ADC input selection: 000 = TSPX 001 = TSMX 010 = TSPY 011 = TSMY 100 = AD0 101 = AD1 110 = AD2 111 = AD3 Rev. 02 — 21 June 2002 UCB1400 and power management monitor …continued D11 D10 ...
Page 45
... ADC conversion is in progress. ‘1’ if the ADC conversion is completed and the ADC data is stored in AD9 - AD0 Reserved. AD9 - AD0 R ADC data. Rev. 02 — 21 June 2002 UCB1400 and power management monitor …continued D11 D10 AD9 AD8 ...
Page 46
... Wake-up signalling via SDATA_IN when BIT_CLK is off Reserved. OVFL RW When read, returns ADC overflow status (set status is sticky until cleared). When written, clears ADC overflow status. Rev. 02 — 21 June 2002 UCB1400 and power management monitor D11 D10 D9 D8 BB0 TR1 TR0 M1 ...
Page 47
... Codec input blocks are always ON. • 3: Smart Low Power Mode on both Codec and PLL. EV2 - EV0 RW Must be set to ‘0’ (other values reserved for testing purposes only). Rev. 02 — 21 June 2002 UCB1400 and power management monitor D11 D10 D9 D8 AVEN1 AVEN0 X ...
Page 48
... Symbol Bit Symbol Table 53: Bit D15 - This register cannot be reset and is not scan testable. It has no effect until the UCB1400 is put in Vendor-Specific Test Mode (refer to 12.22 Extra Interrupt register (index 0x70) Table 54: Register address: 0x70; default: 0000 Bit Symbol Bit Symbol ...
Page 49
... Vendor ID2 register D15 D14 D13 D12 Rev. 02 — 21 June 2002 UCB1400 and power management monitor D11 D10 D11 D10 ...
Page 50
... Line-in selected Audio DAC and headphone driver only Touch screen bias only 10-bit ADC only Standby Rev. 02 — 21 June 2002 UCB1400 Audio codec with touch screen controller and power management monitor Min Max 0 +125 40 +85 1500 +1500 ...
Page 51
... digital input digital input; A-weighted Code = 0; A-weighted kHz; L ripple ripple (p-p) Rev. 02 — 21 June 2002 UCB1400 Audio codec with touch screen controller and power management monitor Min Typ Max 200 1.0 1.0 0.1 0 ...
Page 52
... AD0 AD1 AD2 V = 7.5 V AD3 Non-synchronization mode ( AVE = 0) Synchronization mode; rising edge ADCSYNC to sample moment ( AVE = AVE = 0 Rev. 02 — 21 June 2002 UCB1400 Audio codec with touch screen controller and power management monitor Min Typ Max 1.89 10 2500 7.5 - ...
Page 53
... T Rising edge of RESET to Hi-Z delay off 9397 750 09611 Product data = 25 C; all voltage measured with respect to ground; unless otherwise specified. Conditions Rev. 02 — 21 June 2002 UCB1400 Audio codec with touch screen controller and power management monitor Min Typ Max 1 162 ...
Page 54
... Audio codec with touch screen controller T rst_low RESET BIT_CLK T sync_high SYNC BIT_CLK T clk_high BIT_CLK T T sync_high SYNC Rev. 02 — 21 June 2002 UCB1400 and power management monitor T rst2clk SN00229 T sync2clk SN00230 T clk_low clk_period T sync_low T sync_period SN00231 © Koninklijke Philips Electronics N.V. 2002. All rights reserved. ...
Page 55
... SDATA_IN Trise din SDATA_OUT Trise dout SLOT 1 SYNC BIT_CLK WRITE TO SDATA_OUT 0x26 SDATA_IN BIT_CLK not to scale. Rev. 02 — 21 June 2002 UCB1400 Audio codec with touch screen controller and power management monitor hold SN00232 Tfall clk Tfall sync Tfall din Tfall ...
Page 56
... GPIO( TSPX GPIO( TSPY GPIO( TSMX GPIO(9) 2 XTL_IN 4 DVSS1 7 DVSS2 26 AVSS1 33 AVSS2 3 XTL_OUT 42 AVSS3 Rev. 02 — 21 June 2002 UCB1400 and power management monitor T setup2rst Hi-Z T off SN00235 AVdd +3 0.1 uF 0.1 uF 0.1 uF 0.1 uF 0.1 uF LINE_OUT_L LINE_OUT_R VREFDRV C13 ...
Page 57
... ADC REFERENCE AC LINK I/O AND CONTROL OSC 2-CHANNEL 20-BIT AUDIO DAC DIGITAL 2-CHANNEL I/O 20-BIT AUDIO ADC 3.3V Rev. 02 — 21 June 2002 UCB1400 and power management monitor PROCESSOR HEADPHONES POWERED SPEAKERS CD PLAYER MIC SN00238 © Koninklijke Philips Electronics N.V. 2002. All rights reserved ...
Page 58
... 2 scale (1) ( 0.18 7.1 7.1 9.15 9.15 1.0 0.5 0.12 6.9 6.9 8.85 8.85 REFERENCES JEDEC EIAJ MS-026 Rev. 02 — 21 June 2002 UCB1400 Audio codec with touch screen controller and power management monitor detail X (1) ( 0.75 0.95 0.95 7 0.2 0.12 0.1 0.45 0.55 0.55 0 EUROPEAN ...
Page 59
... Product data parallel to the transport direction of the printed-circuit board; transport direction of the printed-circuit board. Rev. 02 — 21 June 2002 UCB1400 Audio codec with touch screen controller and power management monitor © Koninklijke Philips Electronics N.V. 2002. All rights reserved ...
Page 60
... Product data Suitability of surface mount IC packages for wave and reflow soldering methods [1] [4] , SO, SOJ Rev. 02 — 21 June 2002 UCB1400 Audio codec with touch screen controller and power management monitor Soldering method Wave Reflow not suitable suitable [3] ...
Page 61
... Revision history Rev Date CPCN Description 02 20020621 - Product data; second version; Engineering Change Notice 853-2358 28518; supersedes initial version UCB1400- Jan 2002 (9397 750 09242). Modifications: • Section 2 “Features” • Section 9.2.4 “Headphone driver” • Section 9.5 “Power-down modes” ...
Page 62
... Rev. 02 — 21 June 2002 UCB1400 Audio codec with touch screen controller and power management monitor Fax: + 24825 © Koninklijke Philips Electronics N.V. 2002. All rights reserved. ...
Page 63
... Pinning information 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 7 Functional description . . . . . . . . . . . . . . . . . . . . . . . . 5 7.1 Functional block diagram . . . . . . . . . . . . . . . . . . . . . . ’97 interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 8.1 Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 8.2 Resetting UCB1400 . . . . . . . . . . . . . . . . . . . . . . . . . . 6 8.3 Digital interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 8.3.1 AC-link digital serial interface protocol . . . . . . . . . . . . 7 8.3.2 AC-link audio output frame (SDATA_OUT 8.3.3 AC-link audio input frame (SDATA_IN 8.3.4 AC-link low power mode 8.4 Accessing the UCB1400 . . . . . . . . . . . . . . . . . . . . . 14 8.5 Variable sample rate signaling protocol ...