x28c64 Intersil Corporation, x28c64 Datasheet

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x28c64

Manufacturer Part Number
x28c64
Description
5 Volt, Byte Alterable E2prom
Manufacturer
Intersil Corporation
Datasheet

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© Xicor, Inc. 1991, 1995 Patents Pending
3853-2.7 4/2/96 T0/C3/D2 NS
X28C64
64K
FEATURES
PIN CONFIGURATION
V SS
I/O 0
I/O 1
I/O 2
A 12
NC
A 7
A 6
A 5
A 4
A 3
A 2
A 1
A 0
150ns Access Time
Simple Byte and Page Write
—Single 5V Supply
—Self-Timed
Low Power CMOS
—60mA Active Current Max.
—200 A Standby Current Max.
Fast Write Cycle Times
—64 Byte Page Write Operation
—Byte or Page Write Cycle: 5ms Typical
—Complete Memory Rewrite: 0.625 sec. Typical
—Effective Byte Write Cycle Time: 78 s Typical
Software Data Protection
End of Write Detection
—DATA Polling
—Toggle Bit
High Reliability
—Endurance: 100,000 Cycles
—Data Retention: 100 Years
JEDEC Approved Byte-Wide Pinout
—No External High Voltages or V
—No Erase Before Write
—No Complex Programming Algorithms
—No Overerase Problem
PLASTIC DIP
FLAT PACK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Circuits
CERDIP
X28C64
SOIC
28
27
26
25
24
23
22
21
20
19
18
17
16
15
3853 FHD F02
V CC
WE
NC
A 8
A 9
A 11
OE
A 10
CE
I/O 7
I/O 6
I/O 5
I/0 4
I/O 3
I/O 0
NC
A 6
A 5
A 4
A 3
A 2
A 1
A 0
5
6
7
8
9
10
11
12
13
14 15 16 17 18 19 20
4
5 Volt, Byte Alterable E
3
PLCC
2
X28C64
LCC
PP
1 32 31 30
Control
29
28
27
26
25
24
23
22
21
3853 FHD F03
X28C64
A 8
A 9
A 11
NC
OE
A 10
CE
I/O 7
I/O 6
1
V SS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
A 10
NC
NC
CE
A 2
A 1
A 0
DESCRIPTION
The X28C64 is an 8K x 8 E
Xicor’s proprietary, high performance, floating gate
CMOS technology. Like all Xicor programmable non-
volatile memories the X28C64 is a 5V only device. The
X28C64 features the JEDEC approved pinout for byte-
wide memories, compatible with industry standard RAMs.
The X28C64 supports a 64-byte page write operation,
effectively providing a 78 s/byte write cycle and en-
abling the entire memory to be typically written in 0.625
seconds. The X28C64 also features DATA and Toggle
Bit Polling, a system software support scheme used to
indicate the early completion of a write cycle. In addi-
tion, the X28C64 includes a user-optional software data
protection mode that further enhances Xicor’s hard-
ware write protect capability.
Xicor E
tions requiring extended endurance. Inherent data re-
tention is greater than 100 years.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
2
PROMs are designed and tested for applica-
2
PROM
X28C64
TSOP
Characteristics subject to change without notice
2
PROM, fabricated with
8K x 8 Bit
3853 ILL F23.1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A 3
A 4
A 5
A 6
A 7
A 12
NC
NC
V CC
NC
WE
NC
A 8
A 9
A 11
OE

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x28c64 Summary of contents

Page 1

... DESCRIPTION The X28C64 Xicor’s proprietary, high performance, floating gate CMOS technology. Like all Xicor programmable non- volatile memories the X28C64 only device. The Control PP X28C64 features the JEDEC approved pinout for byte- wide memories, compatible with industry standard RAMs. ...

Page 2

... No Connect FUNCTIONAL DIAGRAM A 0 –A 12 ADDRESS INPUTS Data In/Data Out (I/O Data is written to or read from the X28C64 through the I/O pins. Write Enable (WE) The Write Enable input controls the writing of data to the X28C64. PIN CONFIGURATION 3853 PGM T01 X BUFFERS LATCHES AND ...

Page 3

... CE is HIGH. Write Write operations are initiated when both CE and WE are LOW and OE is HIGH. The X28C64 supports both a CE and WE controlled write cycle. That is, the address is latched by the falling edge of either CE or WE, whichever occurs last. Similarly, the data is latched internally by the rising edge of either CE or WE, whichever occurs first ...

Page 4

... READY HIGH DATA Polling can effectively halve the time for writing to the X28C64. The timing diagram in Figure 2 illustrates the sequence of events on the bus. The software flow diagram in Figure 3 illustrates one method of implement- ing the routine. NO 3853 FHD F13 4 ...

Page 5

... DATA Polling. This can be especially helpful in an array comprised of multiple X28C64 memories that is frequently updated. Toggle Bit Polling can also provide a method for status checking in multiprocessor applications. The timing diagram in Figure 4 illustrates the sequence of events on the bus ...

Page 6

... This circuit is nonvolatile and will remain set for the life of the device unless the reset command is issued. Once the software protection is enabled, the X28C64 is also protected from inadvertent and accidental writes in the powered-on state. That is, the software algorithm must be issued prior to writing additional data to the device ...

Page 7

... PAGE Regardless of whether the device has previously been protected or not, once the software data protection algorithm is used and data has been written, the X28C64 will automatically disable further writes unless another command is issued to cancel it further commands are issued the X28C64 will be write protected during power-down and after any subsequent power-up ...

Page 8

... E PROM programmer, the following six step algo- rithm will reset the internal protection circuit. After t the X28C64 will be in standard operating mode. Note: Once initiated, the sequence of write opera- tions should not be interrupted. 3853 ILL F19.2 ...

Page 9

... X28C64 SYSTEM CONSIDERATIONS Because the X28C64 is frequently used in large memory arrays provided with a two line control architecture for both read and write operations. Proper usage can provide the lowest possible power dissipation and elimi- nate the possibility of contention where multiple I/O pins share the same bus ...

Page 10

... X28C64 ABSOLUTE MAXIMUM RATINGS* Temperature under Bias X28C64 ........................................ – +85 C X28C64I, X28C64M ................... – +135 C Storage Temperature ....................... – +150 C Voltage on any Pin with Respect ....................................... D.C. Output Current ............................................. 5mA Lead Temperature (Soldering, 10 seconds) .............................. 300 C RECOMMENDED OPERATING CONDITIONS Temperature Min. Commercial ...

Page 11

... X28C64 ENDURANCE AND DATA RETENTION Parameter Minimum Endurance Data Retention POWER-UP TIMING Symbol (3) t Power-up to Read Operation PUR (3) t Power-up to Write Operation PUW CAPACITANCE 1MHz Symbol (3) C Input/Output Capacitance I/O (3) C Input Capacitance IN A.C. CONDITIONS OF TEST Input Pulse Levels ...

Page 12

... return HIGH (whichever occurs first) to the time when the outputs are no longer driven X28C64-15 Min. 150 OLZ t LZ DATA VALID are periodically sampled and not 100% tested. t OHZ 12 X28C64-20 X28C64-25 Max. Min. Max. Min. Max. 200 250 150 200 250 150 200 250 70 80 100 0 0 ...

Page 13

... X28C64 WRITE CYCLE LIMITS Symbol Parameter (5) t Write Cycle Time WC t Address Setup Time AS t Address Hold Time AH t Write Setup Time CS t Write Hold Time CH CE Pulse Width HIGH Setup Time t OES OE HIGH Hold Time t OEH WE Pulse Width t WP ...

Page 14

... X28C64 CE Controlled Write Cycle ADDRESS OES DATA IN DATA OUT Page Write Cycle ( (9) ADDRESS * I/O BYTE 0 *For each successive write within the page write operation –A 12 should be the same or writes to an unknown address could occur. ...

Page 15

... X28C64 DATA Polling Timing Diagram (10 ADDRESS I/O 7 (10) Toggle Bit Timing Diagram OEH OE HIGH Z I Starting and ending state of I/O 6 will vary, depending upon actual Note: (10) Polling operations are by definition read cycles and are therefore subject to read cycle timings. ...

Page 16

... X28C64 NOTES 16 ...

Page 17

... X28C64 PACKAGING INFORMATION 28-LEAD PLASTIC DUAL IN-LINE PACKAGE TYPE P PIN 1 INDEX PIN 1 SEATING PLANE 0.150 (3.81) 0.125 (3.17) 0.110 (2.79) 0.090 (2.29) TYP. 0.010 (0.25) NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 1.460 (37.08) 1.400 (35.56) 0.550 (13.97) 0.510 (12.95) 1.300 (33.02) REF. 0.085 (2.16) 0.040 (1.02) 0.160 (4.06) 0.125 (3.17) 0.030 (0.76) 0.015 (0.38) 0.062 (1.57) 0.020 (0.51) 0.050 (1.27) ...

Page 18

... X28C64 PACKAGING INFORMATION 28-LEAD HERMETIC DUAL IN-LINE PACKAGE TYPE D SEATING 0.200 (5.08) 0.125 (3.18) NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 1.490 (37.85) 1.435 (36.45) PIN 1 1.30 (33.02) REF. PLANE 0.070 (1.78) 0.030 (0.76) 0.110 (2.79) TYP. 0.055 (1.40) 0.090 (2.29) TYP. 0.100 (2.54) 0.620 (15.75) 0.590 (14.99) TYP. 0.614 (15.60) TYP. 0.010 (0.25) 18 0.610 (15.49) 0.500 (12.70) 0.100 (2.54) 0.035 (0.89) ...

Page 19

... X28C64 PACKAGING INFORMATION 32-LEAD PLASTIC LEADED CHIP CARRIER PACKAGE TYPE J 0.420 (10.67) 0.045 (1.14 0.495 (12.57) 0.485 (12.32) TYP. 0.490 (12.45) 0.453 (11.51) 0.447 (11.35) TYP. 0.450 (11.43) 0.300 (7.62) PIN 1 0.050 (1.27) TYP. 0.021 (0.53) 0.013 (0.33) TYP. 0.017 (0.43) REF. 0.595 (15.11) 0.585 (14.86) TYP. 0.590 (14.99) 0.553 (14.05) 0.547 (13.89) TYP. 0.550 (13.97) 0.400 REF. (10.16) NOTES: 1 ...

Page 20

... X28C64 PACKAGING INFORMATION 28-LEAD PLASTIC SMALL OUTLINE GULL WING PACKAGE TYPE S 0.1040 (2.6416) 0.0940 (2.3876) 0 – 8 NOTES: 1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 2. FORMED LEAD SHALL BE PLANAR WITH RESPECT TO ONE ANOTHER WITHIN 0.004 INCHES 3. BACK EJECTOR PIN MARKED “KOREA” 4. CONTROLLING DIMENSION: INCHES (MM) ...

Page 21

... X28C64 PACKAGING INFORMATION 32-PAD CERAMIC LEADLESS CHIP CARRIER PACKAGE TYPE E PIN 1 0.200 (5.08) BSC 0.028 (0.71) 0.022 (0.56) (32) PLCS. 0.458 (11.63) 0.442 (11.22) 0.458 (11.63) 0.300 (7.62) NOTE: 1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 2. TOLERANCE: 1% NLT 0.005 (0.127) 0.150 (3.81) BSC 0.020 (0.51 REF. 0.095 (2.41) 0.075 (1.91) 0.022 (0.56) 0.006 (0.15) 0.055 (1.39) 0.045 (1.14) TYP ...

Page 22

... X28C64 PACKAGING INFORMATION 28-LEAD CERAMIC PIN GRID ARRAY PACKAGE TYPE K TYP. 0.100 ALL LEADS PIN 1 INDEX 0.660 (16.76) 0.640 (16.26) NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS 0.080 0.080 0.070 ...

Page 23

... X28C64 PACKAGING INFORMATION 0.740 (18.80) MAX. 0.006 (0.15) 0.003 (0.08) TYP. 0.300 2 PLCS. NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 28-LEAD CERAMIC FLAT PACK PIN 1 INDEX 1 0.440 (11.18) MAX. 0.370 (9.40) 0.250 (6.35) 0.180 (4.57) MIN. 0.030 (0.76) MIN. 23 0.019 (0.48) 0.015 (0.38) 28 0.050 (1.27) BSC 0.045 (1.14) MAX. 0.130 (3.30) 0.090 (2.29) 0.045 (1.14) 0.025 (0.66) 3926 FHD F16 ...

Page 24

... X28C64 PACKAGING INFORMATION SEE NOTE 2 8.02 (0.315) 7.98 (0.314) 1.18 (0.046) 1.02 (0.040) 0.58 (0.023) 0.42 (0.017) SOLDER PADS FOOTPRINT NOTE: 1. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS (INCHES IN PARENTHESES). 32-LEAD THIN SMALL OUTLINE PACKAGE (TSOP) TYPE T SEE NOTE 2 12.50 (0.492) 12.30 (0.484) PIN #1 IDENT. O 0.76 (0.03) 14.15 (0.557) 13.83 (0.544) 14.80 ± 0.05 (0.583 ± 0.002) 0.30 ± ...

Page 25

... A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system affect its safety or effectiveness. X28C64 Access Time – ...

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